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參數(shù)資料
| 型號： | VT86C100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI FAST ETHERNET CONTROLLER |
| 中文描述： | PCI快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 349K |
| 代理商： | VT86C100A |
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VIA Technologies, Inc.
Preliminary VT86C100A
10
9
8
CRS
OWC
ABT
TSR0
Carrier Sense lost
bit is set when the carrier is lost during the transmission of a packet.
Late Collisions :
This bit is set when late collision occurred.
Transmit Abort :
transmit module abort after excessive collision.
Transmit Status Register 0
CD heartbeat :
this bit only effective in 10Base-T mode. When set, this bit
indicates a heartbeat collision check failure.
Collision retry count :
this 4-bits counter indicates the number of collisions that
occurred
7-0
FIFO under-flow :
this bit set indicates that the transmitter aborted by transmit
FIFO encountered an empty while transmitting a frame.
Deferred:
When set, indicates that the VT86C100A had to defer while ready to
transmit a frame because carrier was asserted.
6.2.3. T
RANSMIT
D
ESCRIPTOR
1 (TDES1)
DES1 contain the transmit status, the frame length and the descriptor ownership information.
Transmit Configure Register
Interrupt Control
: This bit support for interrupt PACEing , set 1 mean the
VT86C100A received this descriptor will generate the interrupt.
End of Packet :
End of Packet buffer
Start of Packet :
In descriptor ring structure, STP=EDP=1 single buffer
descriptor, or chained buffer structure be follows :
STP EDP Description
1 1 Single buffer descriptor
1 0 First buffer descriptor, further buffer chained
0 1 Chained buffer packet end
0 0 X
CRC disable :
The VT86C100A transmitter will disable generated the CRC
when this set 1.
Chain
: Chain buffer
Extend Fragment of Frame Length
: must be zero now.
Transmit buffer size :
the fragment of frame buffer size
6.3 Buffer Structure and Interrupt Control
data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers
contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by
Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]
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相關代理商/技術參數(shù) |
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| VT86C926 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMAZON PCI ETHERNET CONTROLLER |
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| VT905GA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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