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| 型號： | VSLI2002_1MB_MRAM |
| 英文描述： | A low power 1Mbit MRAM based on 1T1MTJ bit cell integration with copper interconnects |
| 中文描述： | 甲低功耗1Mbit的基礎(chǔ)上1T1MTJ的MRAM位單元集成銅互連 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 246K |
| 代理商： | VSLI2002_1MB_MRAM |
To be published at VLSI Symposium 2002
A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper
Interconnects
M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G.
Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani
Motorola Labs and Motorola Semiconductor Products Sector
7700 S. River Parkway
Tempe, AZ 85284
Abstract
A low power 1Mb Magnetoresistive Random Access
Memory (MRAM) based on a 1-Transistor and 1-Magnetic
Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is
the largest MRAM memory demonstration to date. In this
circuit, MTJ elements are integrated with CMOS using
copper interconnect technology. The copper interconnects
are cladded with a high permeability layer which is used to
focus magnetic flux generated by current flowing through the
lines toward the MTJ devices and reduce the power needed
for programming the bits. The 25mm
2
1Mb MRAM circuit
operates with address access times of less than 50ns,
consuming 24mW at 3.0V and 20MHz. The circuit is
fabricated in a 0.6
μ
m CMOS process utilizing five layers of
metal and two layers of poly.
Introduction
Magnetoresistive
Random
(MRAM) is a high-speed, low-voltage, high-density,
nonvolatile memory with unlimited read/write endurance. A
512b and 256kb MRAM based on 1T1MTJ
1,2
and a 1kb
MRAM based on 2T2MTJ
3
have been previously reported in
the literature. This paper reports the first demonstration of a
1T1MTJ 1Mb MRAM.
The magnetic tunnel junction (MTJ) material stack
(Fig. 1) is composed of two magnetic layers separated by a
thin AlOx dielectric barrier. A
layer of antiferromagnetic
material with strong exchange coupling, such as FeMn or
IrMn, is in contact with the bottom magnetic layer, pinning it
in one direction. This layer is separated from the next
magnetic layer by a thin layer of Ru, creating a synthetic
antiferromagnet (SAF). The strong exchange between the
magnetic layers in the SAF structure fixes the magnetic
polarization of the fixed layer in one direction and prevents
the fixed layer from switching during write operations.
The polarization of the top magnetic layer is free to
rotate and is thus called the free layer. The resistance of the
memory bit is either low or high dependent on the relative
polarization, parallel or anti-parallel, of the free layer with
respect to the fixed layer
4
. The switching of the free layer
between the two polarization states is hysteretic, giving the
device two stable memory states. Topological roughness of
the magnetic layers causes a weak ferromagnetic coupling
shifting the hysteresis loop. The SAF structure provides a
Access
Memory
mechanism for adjusting the magnetostatic charge of the
bottom magnetic electrode, enabling the hysteresis loop to be
centered by adjusting the balance of the SAF layers,
canceling out the topological coupling.
Base electrode
AlOx
AF pinning layer
Pinned
Ru
Fixed Layer
Free Layer
Top electrode
SAF
}
Fig. 1. MTJ Material Stack with Synthetic Antiferromagnet (SAF)
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
-75
-50
-25
0
25
50
75
Easy Axis Field (Oe)
R
-
μ
m
2
)
44%
change
Fig. 2. Hysteresis loop of 0.6x1.2
μ
m
2
device at low bias.
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