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參數(shù)資料
| 型號(hào)： | VSC834UB |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | VSC834UB |
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VITESSE
Data Sheet
VSC834
2.5Gb/s 17x17 Crosspoint Switch
with Input Signal Activity (ISA) Monitoring
Page 6
G52247-0, Rev 4.3
06/01/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 4: Program Timing
Table 4: Programing Port Interface Timing
Note 1: Measured from falling edge.
Note 2: Measured from rising edge.
Parameter
Description
Min
Max
Units
T
config
T
pdADDR
T
pdRDB
T
pdint
T
pdstate
T
sRDB
T
hRDB
T
sWRB
T
hWRB
T
sCONFIG
T
sCSB
T
pwCONFIG
T
pwWRB
T
pwRDB
T
tsDATA
T
sALE
Switch configuration delay
Data read propagation delay from ADDR
Data read propagation delay from RDB
(1)
Interrupt propagation delay from MONCLK
(2)
MONCLK to internal state register change delay
(2)
ADDR to RDB setup time
RDB to ADDR hold time
WRB setup time (for either ADDR or DATA)
WRB hold time (for either ADDR or DATA)
WRB to CONFIG setup time
CSB setup time (to either WRB or RDB)
CONFIG pulse width (high)
WRB pulse width (low and high)
RDB pulse width (low and high)
DATA tri-state delay (from either RDB or CSB)
(2)
ALE setup time (for multiplexed ADDR/DATA bus)
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
7
50
6
5
3
5
3
1
0
10
10
10
10
5
ADDR[5:0]
DATA[4:0]
CSB
WRB
RDB
CONFIG
T
sCSB
T
sWRB
T
hWRB
T
sCONFIG
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