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參數(shù)資料
| 型號： | VSC8132QR |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488Gb/s 1:32 SONET/SDH Demux |
| 中文描述： | MUX/DEMUX, PQFP128 |
| 封裝： | 14 X 20 MM, 2 MM HEIGHT, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 121K |
| 代理商： | VSC8132QR |
VITESSE
Preliminary Data Sheet
VSC8132
2.488Gb/s 1:32 SONET/SDH Demux
G52250-0, Rev 3.1
12/7/00
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
2.488Gb/s 1:32 Demultiplexer
SONET STS-48/SDH STM-16
HSPECL Differential Serial Data and Clock
Inputs
32-Bit TTL Parallel Data Outputs with Odd/
Even Parity Check
Frame Detect Synchronization
General Description
The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL
77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock
(CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz,
and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is per-
formed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output
(PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via
the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data
steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame
Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the
activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM,
CKALARM).
Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a ther-
mally-enhanced 128-pin, 14x20x2mm PQFP package.
VSC8132 Block DIagram
77.76, 51.84, and 38.88MHz TTL Clock Outputs
Single 3.3V supply
Loss of Clock Alarm
Loss of Data Alarm
2.05W Max Power Dissipation
128-Pin PQFP Package
Framing
and
Parity
DATA[3:0]
SYNC
PARITY
Clock
Generation
Alarms
1:32
Demux
DATACLK78
CLK51
CLK38
DTALARM
CKALARM
RESET
PARSEL
OOFN
DI+
DI–
CLKI+
CLKI–
ALMRESET
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