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參數(shù)資料
| 型號(hào)： | VSC8021FI |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| 中文描述： | 容量高達(dá)2.5GB / s的SONET的兼容8位/解復(fù)用器芯片組 |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大小： | 220K |
| 代理商： | VSC8021FI |
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VITESSE
Data Sheet
VSC8021/VSC8022
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
Page 4
G52028-0, Rev 4.1
05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VSC8021 Multiplexer AC Characteristics
(Over recommended operating conditions)
Figure 3: VSC8021 Multiplexer Waveforms
Table 1: VSC8021 Multiplexer AC Characteristics
(over recommended operating conditions)
NOTES: (1) The parts are guaranteed by design to operate from DC to a maximum frequency of 2.5GHz.
(2) Required when SYNC not connected to ERR.
Parameter
Description
Min
Typ
Max
Units
Conditions
t
C
t
D
t
DSU
t
DH
Clock period
(1)
400
ps
BYTE clock period (t
D
= t
C
x 8)
Parallel data set-up time
3.2
ns
0.6
ns
Data hold time
1.4
ns
t
CMD
High-speed clock output (CO, CON) timing, falling
edge of CO to muxed data output, (DO, DON) timing
Byte clock to CLK8 timing
(2)
220
350
ps
t
BCLK8
0.5
1.0
1.5
ns
Jitter (p-p)
CLKI, CLKIN to DO, DON (max-min), (HI to LO),
same part, same pin at constant conditions
<50
ps
t
D
t
C
VALID DATA(2)
t
DH
Serialized Byte 1
D01
D02
D03
D04
D05
D06
D07
D08
t
DSU
VALID DATA(1)
t
CMD
NOTES:
= Don’t care.
period x 8 =
period.
CLKI (CLKIN)
BYCLK (BYCLKN)
(1) Negative edge is active edge.
(2) BYCLK/CLK8 timing required when SYNC not connected to ERR.
tBCLK8
High speed differential clock input
D1-D8, D1N-D8N
Parallel differential data inputs
CO, CON
DO,DON
Byte clock input
CLK8
High speed differential clock outputs
High speed differential data outputs
SYNC
CLK8 adjustment input
CLKI , CLKIN
(1)
BYCLK (BYCLKN)
(1)
Phase adjustable
÷
8 output
(2)
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