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參數(shù)資料
| 型號： | VSC6250QW |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 1Gb/s 16-Channel Drive-Side Deskew IC |
| 中文描述： | 1GB / s的16通道驅(qū)動器側(cè)偏移校正集成電路 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 240K |
| 代理商： | VSC6250QW |
VITESSE
Data Sheet
VSC6250
1Gb/s 16-Channel
Drive-Side Deskew IC
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52197-0, Rev. 4.0
8/19/00
The delay of each of the deskewed outputs can be adjusted separately to compensate for differences in path
length between DUTs on a single test head. The maximum delay is 7ns. Delay span is 5ns. Usable range is a
minimum of 4ns
(1)
.
Resolution is 8ps. To compensate for pulse dispersion in pin electronics, delay of the rising
and falling edges can be adjusted independently.
To ensure timing performance, delay of the VSC6250 is measured in production at every time step of every
vernier. Figure 3 shows measured output waveforms of the VSC6250. Figure 3 (a) shows a measured minimum
output pulse width. The specified mimimum output pulse width is 500ps, but this measurement shows operation
down to 300ps. Figure 3 (b) shows typical timing resolution of 8ps.
Figure 3: VSC6250 Measured Output Waveforms
a) Mininum output pulse width of 300ps
(b) Typical timing resolution of 8ps
With next generation testers required to test more DUTs per testhead in the same footprint, board area is a
critical design parameter. Providing 16 deskew channels in a 14mmx20mm thermally-enhanced 128-pin PQFP
package, the VSC6250 consumes less than 1/2 the total board area of the bipolar alternative.
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