參數(shù)資料
型號: VS6524Q06J
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁數(shù): 14/70頁
文件大?。?/td> 505K
代理商: VS6524Q06J
Operational modes
VL6524/VS6524
14/70
During the power-up sequence (CE = logic 1)
The digital supplies must be on and stable.
The internal digital supply of the VL6524/VS6524 is enabled by an internal switch
mechanism.
All internal registers are reset to default values by an internal power on reset cell.
Figure 3.
Power up sequence
STANDBY mode:
The VL6524/VS6524 enters STANDBY mode when the CE pin on the
device is pulled HIGH. Power consumption is very low, most clocks inside the device are
switched off.
In this state I2C communication is possible when CLK is present and when the
microprocessor is enabled by writing the value 0x06 to the MicroEnable register 0xC003
(
Table 7
).
All registers are reset to their default values. The device I/O pins have a very high-
impedance.
Note:
On exit from STANDBY mode, the VL6524/VS6524 is in a transient mode called
UNINITIALISED, this mode is not a user mode.
STOP mode:
This is a low power mode. The analogue section of the VL6524/VS6524 is
switched off and all registers are accessed over the I2C interface. A run command received
in this state automatically sets a transition through the PAUSE state to the run mode.
PAUSE mode:
In this mode all VL6524/VS6524 clocks are running and all registers are
accessible but no data is output from the device. The device is ready to start streaming but
is halted. This mode is used to set up the required output format before outputting any data.
Note:
The PowerManagement register bTimeToPowerdown can be adjusted in PAUSE mode but
has no effect until the next RUN to PAUSE transition (
Table 13
).
RUN mode:
This is the fully operational mode.
CE
CLK
AVDD (2.8V)
VDD (1.8V/2.8V)
SDA
SCL
t1
t2
t3
t4
t1 >= 0ns
t2 >= 0ns
t3 >= 0ns
t4 >= 25ms
Constraints:
t5
low level command:enable clocks
setup commands
t5 >= 2ms
standby
POWER DOWN
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