參數(shù)資料
型號: VRS550
廠商: Electronic Theatre Controls, Inc.
英文描述: VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述: VRS550 - 8KB閃存,256B的RAM,25MHz的,8位微控制器VRS560 - 16kB的閃存,256B的RAM,25MHz的,8位微控制器
文件頁數(shù): 21/40頁
文件大?。?/td> 868K
代理商: VRS550
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
21
If both conditions are met, the stop bit goes into RB8,
the 8 data bits go into SBUF, and RI is activated. If one
of these conditions is not met, the received frame is
completely lost. At this time, whether the above
conditions are met or not, the unit goes back to
searching for a one to zero transition in RXD.
Mode 2
In Mode 2 a total of 11 bits are transmitted through
TXD or received through RXD. The transactions are
composed of: a Start bit (Low), 8 data bits (LSB first), a
programmable 9
th
data bit, and one Stop bit (High).
For transmission, the 9
th
data bit comes from the TB8
bit of SCON. For example, the parity bit P in the PSW
could be moved into TB8.
In the case of receive, the 9
th
data bit is automatically
written into RB8 of the SCON register.
In Mode 2, the baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
F
IGURE
19:
S
ERIAL
P
ORT
M
ODE
2 B
LOCK
D
IAGRAM
Internal Bus
SBUF
D
S
Q
ZERO DETECTOR
CLK
1
Write to
SBUF
TX Control Unit
Start
TX Clock
Data
Send
RX Control Unit
RI
TI
RX Clock
Control
Start
SHIFT
9-Bit Shift Register
SBUF
Internal Bus
READ SBUF
LOAD SBUF
Serial Port
Shift
DeBit
÷16
÷16
1-0 Transition
Detector
RXD
÷2
Fosc/2
SMOD
0
1
Load
SBUF
Shift
TXD
Stop
Sample
Mode 3
In Mode 3, 11 bits are transmitted through TXD or
received
through
RXD.
composed of: a Start bit (Low), 8 data bits (LSB first),
a programmable 9
th
data bit, and one Stop bit (High).
Mode 3 is identical to Mode 2 in all respects but one;
the baud rate. Either Timer 1 or Timer 2 generates the
baud rate in Mode 3.
The
transactions
are
F
IGURE
20:
S
ERIAL
P
ORT
M
ODE
3 B
LOCK
D
IAGRAM
Internal Bus
SBUF
D
S
Q
ZERO DETECTOR
CLK
1
WSBUF
TX Control Unit
Start
TX Clock
Data
Send
RX Control Unit
RI
TI
RX Clock
Start
SHIFT
9-Bit Shift Register
SBUF
Internal Bus
READ SBUF
LOAD SBUF
Serial Port
Interrupt
Shift
Bit
Detector
÷16
÷16
1-0 Transition
Detector
RXD
÷2
Timer 2
Overflow
Timer 1
RCLK
TCLK
SMOD
0 1
0
1
0
1
Load
SBUF
Shift
TXD
SAMPLE
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