參數(shù)資料
型號(hào)： VRS550-QAI25
廠商： Electronic Theatre Controls, Inc.
英文描述： VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述： VRS550 - 8KB閃存，256B的RAM，25MHz的，8位微控制器VRS560 - 16kB的閃存，256B的RAM，25MHz的，8位微控制器
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 868K
代理商： VRS550-QAI25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
9
Input/Output Ports
The VRS550 and VRS560 have a total of 32 bi-
directional I/O lines grouped in four 8-bit I/O ports.
These I/Os can be individually configured as input or
output
Except for the P0 I/Os, which are of the open drain
type, each I/O is made of a transistor connected to
ground and a weak pull-up resistor.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to ground, this will bring the
I/O to a LOW level.
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case
the pull-up resistor will bring the corresponding pin to a
HIGH level.
To use a given I/O as an input, one must write a 1 into
its associated port register bit.
By default, upon reset all the I/Os are configured as
input.
General Structure of an I/O Port
The following elements establish the link between the
core unit and the pins of the microcontroller:
Special Function Register (same name as port)
Output Stage Amplifier (the structure of this
element varies with its auxiliary function)
From the next figure, one can see that the D flip-flop
stores the value received from the internal bus after
receiving a write signal from the core. Also, note that
the Q output of the flip-flop can be linked to the internal
bus by executing a read instruction.
This is how one would read the content of the register.
It is also possible to link the value of the pin to the
internal bus. This is done by the “read pin” instruction.
In short, the user may read the value of the register or
the pin.
F
IGURE
6:
I
NTERNAL
S
TRUCTURE OF
O
NE OF THE
E
IGHT
I/O P
ORT
L
INES
D Flip-Flop
Output
Stage
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
Structure of the P1, P2, P3
The following figure gives a general idea of the
structure P1, P2 and P3 ports. Note that the figure
below does not show the intermediary logic that
connects the output of the register and the output stage
together because this logic varies with the auxiliary
function of each port.
F
IGURE
7:
G
ENERAL
S
TRUCTURE OF THE
O
UTPUT
S
TAGE OF
P1, P2
AND
P3
D Flip-Flop
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
Vcc
Pull-up
Network
X1
Each line may be used independently as a logical
input or output. When used as an input, as mentioned
earlier, the corresponding port register bit must be
high.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VRS550-QLC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS550-QLI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
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