- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359412 > VPX322XE (MICRONAS SEMICONDUCTOR HOLDING AG) Video Pixel Decoders PDF資料下載
參數(shù)資料
| 型號： | VPX322XE |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 567K |
| 代理商： | VPX322XE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADVANCE INFORMATION
VPX 322xE
17
Micronas
2.6.2. Skew Correction
The VPX delivers orthogonal pixels with a fixed clock
even in the case of non-broadcast signals with substan-
tial horizontal jitter (VCRs, laser disks, certain portions
of the 6 o
’
clock news...).
This is achieved by highly accurate sync slicing com-
bined with post correction. Immediately after the analog
input is sampled, a horizontal sync slicer tracks the posi-
tion of sync. This slicer evaluates, to within 1.6 ns, the
skew between the sync edge and the edge of the pixel-
clock. This value is passed as a skew on to the phase
shift filter in the resizer. The skew is then treated as a
fixed initial offset during the resizing operation.
The skew
block in the resizer performs programmable
phase shifting with subpixel accuracy. In the luminance
path, a linear interpolation filter provides a phase shift
between 0 and 31/32 in steps of 1/32. This corresponds
to an accuracy of 1.6 ns. The chrominance signal can be
shifted between 0 and 7/8 in steps of 1/8.
2.6.3. Peaking and Coring
The horizontal resizer comes with an extra peaking filter
for sharpness control. The center frequency of the peak-
ing filter is automatically adjusted to the image size in
512 steps. However, for each size, the user can select
between a low, middle (default), or high center frequen-
cy for peaking. The peaking amplitude can be controlled
by the user in 8 steps via FP-RAM 0x126/130. Fig. 2
–
15
shows the magnitude response of the eight steps of the
peaking filter corresponding to an image size of 320 pix-
els.
After the peaking filter, an additional coring filter is imple-
mented to the horizontal resizer. The coring filter sub-
tracts 0, 1/2, 1, or 2 LSBs of the higher frequency part of
the signal. Note, that coring can be performed indepen-
dently of the peaking value adjustment.
Fig. 2
–
15:
Frequency response of peaking filter
10
–
10
–
20
–
30
MHz
0
1
3
4
6
0
2
5
dB
2.6.4. YC
b
C
r
Color Space
The color decoder outputs luminance and one multi-
plexed chrominance signal at a sample clock of
20.25 MHz. Active video samples are flagged by a sepa-
rate reference signal. Internally, the number of active
samples is 1080 for all standards (525 lines and 625
lines). The representation of the chroma signals is the
ITU-R 601 digital studio standard.
In the color decoder, the weighting for both color differ-
ence signals is adjusted individually. The default format
has the following specification:
–
Y = 224*Y + 16 (pure binary),
–
Cr = 224*(0.713*(R
–
Y)) + 128 (offset binary),
–
Cb= 224*(0.564*(B
–
Y)) + 128 (offset binary).
2.6.5. Video Adjustments
The VPX provides a selectable gain (contrast) and offset
(brightness) for the luminance samples, as well as addi-
tional noise shaping. Both the contrast and brightness
factors can be set externally via I
2
C serial control of FP-
RAM 0x127,128,131, and 132. Fig. 2
–
16 gives a func-
tional description of this circuit. First, a gain is applied,
yielding a 10-bit luminance value. The conversion back
to 8-bit is done using one of four selectable techniques:
simple rounding, truncation,1-bit error diffusion, or 2-bit
error diffusion. Bit[8] in the
‘
contrast
’
-register selects be-
tween the clamping levels 16 and 32.
I
out
= c * I
in
+ b
c = 0...63/32 in 64 steps
b = –127...128 in 256 steps
In the chrominance path, C
b
and C
r
samples can be
swapped with bit[8] in FP-RAM 0x126 or 130. Adjust-
ment of color saturation and gain is provided via FP-
RAM 0x30
–
33 (see section 2.3.5.).
Fig. 2
–
16:
Contrast and brightness adjustment
Rounding
Truncation
1 bit
Err. Diff.
2 bit
Err. Diff.
Contrast
Select
Brightness
FP-RAM
Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
| VQ1001J | Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode |
| VQ1001J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓30V，夾斷電流0.83A的N溝道增強(qiáng)型MOSFET) |
| VQ1004J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.46A的N溝道增強(qiáng)型MOSFET晶體管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3478 | 制造商:CPI 制造商全稱:CPI 功能描述:X-Band Transmitter |
| VPX60-61ZRZ-DA100-XXP1 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VPX641U025E1L1C | 制造商:Mallory 功能描述:RL764X025 |
| VPX66-611KR-00000-XWL1 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VPX66-611XR-CS1Y3-XXP2 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。