參數(shù)資料
型號: VPX3224E
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁數(shù): 72/92頁
文件大?。?/td> 616K
代理商: VPX3224E
ADVANCE INFORMATION
VPX 322xE
MICRONAS INTERMETALL
72
I
2
C-Registers VPX Back-End
Name
Default
Function
Mode
Number
of Bits
Address
Hex
h’F9
8
w/r
Pad Driver Strength – TTL Output Pads Typ B
DRIVER_B
bit[2:0] :
Driver strength of Port B[7:0]
strb1
bit[5:3] :
Driver strength of HREF, VREF, FIELD, and LLC2
strb2
bit[7:6] :
reserved (must be set to zero)
h’F2
8
w/r
Output Enable
OENA
bit[0] :
1
0
Enable Video Port A
Disable / High Impedance Mode
aen
bit[1] :
1
0
Enable Video Port B
Disable / High Impedance Mode
ben
bit[2] :
1
0
Enable Pixclk Output
Disable / High Impedance Mode
clken
bit[3] :
1
0
Enable HREF, VREF, FIELD, VACT, LLC, LLC2
Disable / High Impedance Mode
zen
bit[4]
1
Enable LLC2 to TDO pin
(if JTAG interface is in Test-Logic-Reset State)
Disable LLC2
0
llc2en
bit[5] :
1
0
no delay of OEQ input signal
1 LLC cycle delay of OEQ input signal (if bit [6] = 1)
oeqdel
bit[6] :
1
0
latch OEQ input signal with rising edge of LLC
don’t latch OE input signal
latoeq
bit[7] :
1
disable OE pin function
oeq_dis
h’AA
8
w/r
Low power mode, LLC mode
LLC
bit[1:0] :
Low power mode
active mode, outputs enabled
outputs tri-stated; clock divided by 2, I
2
C full speed
outputs tri-stated; clock divided by 4, I
2
C full speed
outputs tri-stated; clock divided by 8, I
2
C < 100 kbit/s
00
01
10
11
lowpow
bit[2] :
I
2
C reset
iresen
bit[3] :
1
0
connect LLC2 to TDO pin
connect bit[4] to TDO pin
llc2
bit[4] :
if bit[3] then bit[4] defines LLC2 polarity
else bit[4] is connected to TDO pin
llc2_pol
bit[5] :
switch-off slicer
(if slowpow = 1 then all slicer registers are reset).
slowpow
bit[6] :
1
0
use old llc timing with long hold time
use new llc timing with shorter hold time
oldllc
bit[7] :
reserved (must be set to zero)
h’AB
8
r
bit[7:0] :
status of Port B
bstatus
相關PDF資料
PDF描述
VPX322XE Video Pixel Decoders
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