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參數(shù)資料
| 型號： | VP1058 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) |
| 中文描述： | 8位，25MHz的，視頻閃速ADC（單5V電源） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 430K |
| 代理商： | VP1058 |
VP1058
ELECTRICAL CHARACTERISTICS DEFINITIONS
Analog Bandwidth
The analog input frequency, at which the spectral power of
the fundamental frequency as determined by Fast Fourier
Transform analysis, is 3dB down on the DC level.
Aperture Delay
The delay between the falling edge of the CONV signal
and the instant at which the analog input is sampled.
Aperture Jitter
The variation between successive samples of the aperture
delay.
Conversion Rate
The maximum rate at which the converter will run.
Differential Non-Linearity (DNL)
The deviation of any code width from an ideal LSB step.
Effective Number of Bits (ENOB)
This is a measure of the dynamic performance which is
calculated from the following expression.:
ENOB = SNR-1.76
6.02
SNR is the signal-to-noise ratio, in decibels, at the test
frequency.
Integral Non-Linearity (INL)
The deviation of the centre of each code from a reference
line which has been determined by a least squares curve fit.
Output Data Delay
The delay between the 50% point of the rising edge of the
CONV signal and the 50% point of any data output change.
Reference Ladder Offset
The voltage error at the ends of the resistor chain caused
by the lead frame and bond wire.
Signal-to-Noise Ratio (SNR)
The ratio of the RMS signal amplitude to the RMS value of
'noise' which is defined as the sum of all other spectral
components including harmonics but excluding DC with a full
scale analog input signal.
Test Levels
Level 1 -
100% production tested
Level 2 -
100% production tested at 25
°
C and sample
tested at specified temperatures
Level 3 -
Sample tested only
Level 4 -
Parameter is guaranteed by design and
characteristics testing
Level 5 -
Parameter is a typical value only
CONVERSION TIMING
Operation of the VP1058 requires that an external clock be
applied to the CONV (convert) pin. This CONV signal
synchronises the sampling, conversion, and output stages of
the devices as shown in the timing diagram (Fig.3).
The analog input is sampled when the comparator array is
latched after a rising edge on the CONV pin. This rising edge
also causes the result of the previous sample to be transferred
to the outputs. Data at the outputs is latched at the same time
as the 255 to 8 encoding of the current sample. Both these
operations are performed on the falling edge of the CONV
signal. This results in a 'pipeline' delay which means that the
digital result of sample 'N' is available for acquisition by
external circuitry whilst sample 'N+2' is being taken.
The time interval between a rising edge on the CONV pin
and the comparators latching is the aperture delay time (t
).
This time may be subject to small variations mainly due to
temperature and component matching. The short term
uncertainty in the aperture delay time is specified by the
aperture jitter (or aperture error). Output data becomes valid
after t
(output data delay). Data remains valid for at least t
HO
(output hold time) after the rising edge of the CONV pin.
Fig.3 Timing diagram
DATA VALID N
DATA VALID N+1
DATA VALID N-1
DATA VALID N-2
SAMPLE
N
SAMPLE
N+1
SAMPLE
N+2
SAMPLE
N+3
PIPELINE DELAY
4V
0V
DATA
OUTPUT
CONV
VIN
tAD
tD
tHO
tpw1
tpw0
tCYC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP1058E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| VP1058FCGDGAS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) |
| VP1058FCGDPAS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) |
| VP1058FCGHPAS | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) |
| VP1058J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
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