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參數(shù)資料
| 型號(hào)： | VP101-3BAGP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | DAC |
| 英文描述： | 30/50MHz 8-BIT CMOS VIDEO DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.015 us SETTLING TIME, 8-BIT DAC, PQFP44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 294K |
| 代理商： | VP101-3BAGP |
VP101
6
APPLICATION NOTES
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels it is
recommended that a doubly terminated 75
load be used
with an R
SET
resistor value of approximately 542
Similarly for generation of RS-170-compatible video, it is
recommended that a singly terminated 75
load be used
with an R
SET
value of about 774
. If the VP101 is not driving
a large capacitive load, there will be negligible difference in
video quality between doubly terminated 75
and singly
terminated 75
loads.t
If driving a large capacitive load (load RC >1/20
II
f
c
) it is
recommended that an output buffer with unloaded gain >2 be
used to drive a doubly terminated 75
load.
COMP Resistor
To optimise the settling time of the VP101, a resistor
may be added in series between the COMP capacitor and
COMP pin. The series resistor damps inductive ringing on
COMP, thus improving settling time.
Non-Video Applications
The VP101 may be used in non-video applications by
disabling the video specific control inputs. REF WHITE
should be a logic ‘0’ while BLANC and SYNC should be a
logic ‘1’. I
SYNC
should be connected to V
AA
or AGND. All
three outputs will have the same full scale output current.
The relationship between R
SET
and full scale output
current (I
OUT
) in this configuration is as follows:
I
out
(mA) = 7968 X
≡
255 LSBs
R
SET
(
)
Note
that 1 LSB
≡
With the data inputs at $00, there is a DC offset current (I
min
)
defined as follows:
I
min
(mA) = 656 X
≡
21 LSBs
V
(V)
R
SET
(
)
Therefore the total full scale output current will be I
OUT
+
I
min
. The REF WHITE input may optionally be used as a
‘force to full scale’ control.
Fig.4 Input/output timing
V
V
REF
(V)
32 X R
SET
(
)
TIMING WAVEFORMS
NOTES
1. Output delay, t
DLY
, measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
2. Settling time, t
s
, measured from the 50% point of full scale transition to the output remaining within
±
1 LSB.
3. Output rise/fall time, t
VRF
, measured between the 10% and 90% points of full scale transition.
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PDF描述 |
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| VP101-3BAHP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BADP | 30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BAHP | 30/50MHz 8-BIT CMOS VIDEO DAC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP101-3BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BADP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5BAHP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:30/50MHz 8-BIT CMOS VIDEO DAC |
| VP101-5MAHP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| VP1-0190 | 制造商:COOPER BUSSMANN 功能描述:Ind Power Wirewound 12.2uH 20% Ferrite 850mA T/R |
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