- 您現在的位置：買賣IC網 > PDF目錄2168 > VMUSIC2 (FTDI, Future Technology Devices International Ltd)MOD USB AUDIO FLASH DRIVE I/F PDF資料下載
參數資料
| 型號： | VMUSIC2 |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | MOD USB AUDIO FLASH DRIVE I/F |
| 產品培訓模塊： | USB Introduction |
| 產品目錄繪圖： | VMUSIC2 |
| 標準包裝： | 5 |
| 附件類型： | USB 音頻模塊 |
| 顏色： | 黑 |
| 適用于相關產品： | 存有音頻文件的 USB 驅動器 |
| 產品目錄頁面： | 634 (CN2011-ZH PDF) |
| 其它名稱： | 768-1004 |
VMusic2 Vinculum VNC1L Module
Datasheet Version 0.98
Future Technology Devices International Ltd. 2007
Page
2.3 SPI Interface Signal Descriptions and Timing Diagrams
Tale Data and Control us ignal Mode ptions I Interace
Pin No.
Name
Type
Description
CLK
Input
I Clock input 12MHz maimum.
4
DI
Input
I erial Data Input
2
D
utput
I erial Data utput
6
C
Input
I Chip elect Input
Figure 2 I lave Data ead Cycle
SPICLK
SPI Data In
SPI Data Out
SPI CS
R/W ADD
D0
D1
D2
D3
D4
D5
D6
D7
1
0
From tart I C must e held high or the entire read cycle and must e taken low or at least one clock period
hphbSIIhR/Wb-pg‘1’hb
the chip. The net it is the address it DD which is used to indicate whether the data register (0) or the status
register (1) is read rom. During the I read cycle a yte o data will start eing output on I Data ut on the net
kyhbMSBhhbkhhphSI
ut should e checked to see i the data read is new data. 0 level here on I Data ut means that the data read
is new data. 1 indicates that the data read is old data and the read cycle should e repeated to get new data.
ememer that C must e held low or at least one clock period eore eing taken high again to continue with the
net read or write cycle.
Figure I lave Data Write Cycle
SPICLK
SPI Data In
SPI Data Out
SPI CS
R/W ADD
D0
D1
D2
D3
D4
D5
D6
D7
1
0
From tart I C must e held high or the entire write cycle and must e taken low or at least one clock period
hphbSIIhR/Wb-pg‘0’hb
to the chip. The net it is the address it DD which is used to indicate whether the data register (0) or the status
register (1) is written to. During the I write cycle a yte o data can e input to I Data In on the net clock cycle
hbMSBhhbkhhphSIOhb
tart
tatus
tart
tatus
相關PDF資料 |
PDF描述 |
|---|---|
| VW-05MR-RL | SIREN 9-28VDC SLOW/FAST |
| VW-35SBR-RL | SIREN 9-28VDC SLOW/FAST |
| W2G115-AE31-15 | FAN TUBEAXIAL 119X38MM 24VDC |
| WA-T247-101E | HEATSINK AND CLIP FOR TO-247 BLK |
| WM-61B102B | MICROPHONE OMNI 6X3.4MM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| VMUSIC3 | 功能描述:界面模塊 USB Host and MP3/WMA Player Module RoHS:否 制造商:4D Systems 產品:Serial Converters 通道/端口數量: 數據速率: 接口類型:USB, UART 工作電源電壓:3.3 V, 5 V 最大工作溫度: |
| VMV120SGR12GM | 制造商:Advanced Micro Devices 功能描述:V-SERIES MOBILE SINGLE CORE V120 25W S1 - Trays |
| VM-V67256-R-SS-.075-12 | 制造商:MISC. SPCR/STNDF/HND 功能描述: |
| VM-V67258-R-SS-.075-12 | 制造商:MISC. SPCR/STNDF/HND 功能描述: |
| VMVC2A100R5 | 制造商:Cooper Crouse-Hinds 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。