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參數(shù)資料
| 型號： | VCT1000B |
| 廠商： | CTS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual Input Timing Module |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DMA18 |
| 封裝： | 50.80 X 50.80 MM, 16.51 MM HEIGHT, DIP-18 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 136K |
| 代理商： | VCT1000B |
Stratum III Timing Module : VCT1000B
Application: Dual Input Timing Module
Page 1 of 8
Rev. “5” 1/20/04
1.0
The VCT1000B is a hitless-switching dual-input stratum 3 low jitter timing module with status
outputs and alarms. Dual 8 kHz references are independently selected to lock a digital phase
lock loop resulting in excellent long and short-term stability. Two control inputs are used to
steer the state machine decisions for the operation of the module. The state machine will enter
and maintain the operation in the free run, holdover, or locked condition. The state machine
operates under the requirements of section 3.4 of the Telcordia GR-1244-CORE. Four status
pins indicate the condition, which the unit is operating, and two alarm outputs indicate the loss of
lock and holdover or free run operation. The signal outputs are the low jitter oscillator output
and the divided 8kHz output. Input phase rearrangement allows the output to remain hitless upon
the switching of the references, regardless of input phase. Dimensions are 2” x 2” x 0.55”. A
state machine is used to assure that switching to a bad reference is not allowed, and that both
references are qualified.
Figure 1 VCT1000B Block Diagram
DESCRIPTION AND APPLICATION
System
Control and
State Machine
Main Status Alarm
Ref 1
Ref 2
Free Run
Holdover
Input Buffer
Phase
Alignment
Reference
Qualification
Input Buffer
Phase
Alignment
Reference
Qualification
Hitless
Switching
MUX
Phase
Detector
Holdover
History and
Digital
Filtering
DAC
Divider
Stratum
III OCXO
Buffer
Buffer
Divider
System control lines to all blocks
CNTL A
CNTL B
REF 1
8 kHz
REF 2
8 kHz
Alarm
Out
Loss of
Lock
Alarm
8 kHz
Output
19.440
MHz
Output
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