參數(shù)資料
型號: VC162373ADL
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
中文描述: LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: 7.50 MM, PLASTIC, SOT-370-1, SSOP-48
文件頁數(shù): 10/17頁
文件大?。?/td> 112K
代理商: VC162373ADL
2004 Feb 05
10
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30
series termination
resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A;
74LVCH162373A
Notes
1.
2.
3.
All typical values are measured at T
amb
= 25
°
C.
Measured at V
CC
= 3.3 V.
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
T
amb
=
40 to +125
°
C
t
PHL
/t
PLH
propagation delay nDn to nQn
see Fig 6 and 10
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
1.2
2.7
3.0 to 3.6
3.0 to 3.6
1.5
1.0
1.5
1.5
1.5
1.0
1.5
1.5
3.0
3.0
2.0
2.0
0.9
0.9
8.5
7.5
9.0
8.0
9.5
8.0
6.0
6.0
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay nLE to nQn
see Fig 7 and 10
t
PZH
/t
PZL
3-state output enable time nOE to nQn
see Fig 8 and 10
t
PHZ
/t
PLZ
3-state output disable time nOE to nQn see Fig 8 and 10
t
W
nLE pulse width HIGH
see Fig 7
t
su
set-up time nDn to nLE
see Fig 9
t
h
hold time nDn to nLE
see Fig 9
t
sk(0)
skew
note 3
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
V
CC
(V)
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