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參數(shù)資料
| 型號： | V8039QCL |
| 廠商： | Abracon Corporation |
| 英文描述： | 38MHz-320MHz Low Phase Noise VCXO |
| 中文描述： | 38MHz - 320MHz低相位噪聲壓控 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 225K |
| 代理商： | V8039QCL |
(Preliminary)
ABV8037/38/39
38MHz-320MHz Low Phase Noise VCXO
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001
www.Abracon.com
9/1/05 Page 2
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
ABV8038 (PECL)
ABV8037 & 39 (CMOS or CMOS)
PIN DESCRIPTIONS
Name
TSSOP
Pin number
1
2
3
4
5
6
7
3x3mm QFN
Pin number
11
12
13
14
15
16
1
Type
Description
VDDANA
XIN
XOUT
SEL2
OE_CTRL
VCON
GNDANA
P
I
O
I
I
I
P
VDD for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Output frequency Selector pin.
Output enable control pin. (See OE_CTRL Logic Levels).
Voltage control input.
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GND connection for output buffer circuitry.
PECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary PECL, LVDS, Or single ended CMOS output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
LP
8
2
-
LM
9
3
-
GNDBUF
Q
10
11
4
5
P
O
VDDBUF
12
6
P
QBAR
GNDBUF
SEL1
SEL0
13
14
15
16
7
8
9
10
O
P
I
I
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