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參數(shù)資料
| 型號(hào)： | V62C3802048LL-45BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 9 X 12 MM, CSP, FBGA-48 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 102K |
| 代理商： | V62C3802048LL-45BI |
Parameter
Symbol
-35
-45
Unit
Note
Read Cycle Time
tRC
35
-
45
-
ns
Address Access Time
tAA
-
35
-
45
ns
Chip Enable Access Time
tACE
-
35
-
45
ns
Output Enable Access Time
tOE
-
20
-
20
ns
OutputHold fromAddress Change
tOH
5
-
5
-
ns
Chip Enable to Output in Low-Z
tCLZ
5
-
5
-
ns
4,5
Chip Disable to Output in High-Z
tCHZ
-
20
-
25
ns
4,5
Output Enable to Output in Low-Z
tOLZ
5
-
5
-
ns
4,5
Output Disable to Output in High-Z
tOHZ
-
15
-
20
ns
4,5
Power-Up Time
tPU
0
-
0
-
ns
5
Power-Down Time
tPD
-
35
-
45
ns
5
Read Cycle (3,9) (Vcc = 2.7 to3.3V, Gnd = 0V, TA = 0
0C to +700C / -400C to +850C)
Write Cycle (3,11) (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Symbol
-35
-45
Unit
Note
Write Cycle Time
tWC
35
-
45
-
ns
Chip Enable to Write End
tCW
30
-
40
-
ns
Address Setup to Write End
tAW
30
-
40
-
ns
Address Setup Time
tAS
0
-
0
-
ns
Write Pulse Width
tWP
30
-
35
-
ns
Write Recovering Time
tWR
0
-
0
-
ns
Data Valid to Write End
tDW
20
-
25
-
ns
Data Hold Time
tDH
0
-
0
-
ns
Write Enable to Output in High-Z
tWZ
-
20
-
25
ns
4,5
Output Active from Write End
tOW
5
-
5
-
ns
4,5
Min Max Min Max
7
Min Max Min Max
V62C3802048L(L)
REV. 1.2 May 2001 V62C3802048L(L)
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