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參數(shù)資料
| 型號： | V62C3162096L-85BI |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 STANDARD SRAM, 85 ns, PBGA48 |
| 封裝： | 9 X 12 MM, FBGA-48 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 114K |
| 代理商： | V62C3162096L-85BI |
V62C3162096L(L)
11
Notes (Write Cycle)
1.
L-version includes this feature.
2.
This Parameter is sampled and not 100% tested.
3.
For test conditions, see AC Test Condition, Figure A.
4.
This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5.
This parameter is guaranteed, but is not tested.
6.
WE is High for read cycle.
7.
CE and OE are LOW for read cycle.
8.
Address valid prior to or coincident with CE transition LOW.
9.
All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
Data Retention Mode
V
DR > 2.0V
Vcc_typ
V
IH
V
IH
VDR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform (L Version Only) (TA = 0
0C to +700C / -400C to +850C)
Data Retention Characteristics (L Version Only)(1)
Parameter
Symbol
Test Condition
Min
Max
Unit
VCC for Data Retention
VDR
CE > VCC - 0.2V
2.0
-
V
Data Retention Current
ICCDR
-
1
A
Chip Deselect to Data Retention Time
tCDR
VIN > VCC - 0.2V or
0
-
ns
Operation Recovery Time(2)
tR
VIN < 0.2V
tRC
-
ns
REV. 1.1 April 2001 V62C3162096L(L)
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