參數(shù)資料
型號: V62C2801024LL-100B
廠商: MOSEL-VITELIC
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 100 ns, PBGA48
封裝: FBGA-48
文件頁數(shù): 6/10頁
文件大?。?/td> 92K
代理商: V62C2801024LL-100B
V62C2801024L(L)
Parameter
Symbol
Unit
Note
Read Cycle Time
tRC
70
-
85
-
100
-
150
-
ns
Address Access Time
tAA
-
70
-
85
-
100
-
150
ns
Chip Enable Access Time
tACE
-
70
-
85
-
100
-
150
ns
Output Enable Access Time
tOE
-
40
-
40
-
50
-
70
ns
OutputHold fromAddress Change
tOH
10
-
10
-
10
-
10
-
ns
Chip Enable to Output in Low-Z
tCLZ
10
-
10
-
10
-
10
-
ns
4,5
Chip Disable to Output in High-Z
tCHZ
-
30
-
35
-
40
-
50
ns
4,5
Output Enable to Output in Low-Z
tOLZ
5
-
5
-
5
-
5
-
ns
4,5
Output Disable to Output in High-Z
tOHZ
-
25
-
30
-
35
-
40
ns
4,5
Power-Up Time
tPU
0
-
0
-
0
-
0
-
ns
5
Power-Down Time
tPD
-
70
-
85
-
100
-
150
ns
5
Read Cycle (3,9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 0
0C to +700C / -400C to +850C)
Write Cycle (3,11) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 0
0C to +700C / -400C to +850C)
Parameter
Symbol
Unit
Note
Write Cycle Time
tWC
70
-
85
-
100
-
150
-
ns
Chip Enable to Write End
tCW
60
-
70
-
80
-
120
-
ns
Address Setup to Write End
tAW
60
-
70
-
80
-
120
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
tWP
50
-
60
-
70
-
100
-
ns
Write Recovering Time
tWR
0
-
0
-
0
-
0
-
ns
Data Valid to Write End
tDW
30
-
35
-
40
-
60
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
0
-
ns
Write Enable to Output in High-Z
tWZ
-
30
-
35
-
40
-
50
ns
4,5
Output Active from Write End
tOW
5
-
5
-
5
-
5
-
ns
4,5
Min Max Min Max Min Max Min Max
-70
-85
-100
5
Min Max Min Max Min Max Min Max
-70
-85
-100
-150
REV. 1.1 April 2001 V62C2801024L(L)
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