參數(shù)資料
型號: V62C2162048L-45T
廠商: MOSEL-VITELIC
元件分類: SRAM
英文描述: 128K X 16 STANDARD SRAM, 45 ns, PDSO44
封裝: TSOP2-44
文件頁數(shù): 10/13頁
文件大?。?/td> 117K
代理商: V62C2162048L-45T
V62C2162048L(L)
Parameter
Sym
Unit
Note
Read Cycle Time
tRC
55
-
70
-
85
-
100
-
ns
Address Access Time
tAA
-
55
-
70
-
85
-
100
ns
Chip Enable Access Time
tACE
-
55
-
70
-
85
-
100
ns
Output Enable Access Time
tOE
-
35
-
40
-
40
-
50
ns
Output Hold from Address Change
tOH
10
-
10
-
10
-
10
-
ns
Chip Enable to Output in Low-Z
tLZ
10
-
10
-
10
-
10
-
ns
4,5
Chip Disable to Output in High-Z
tHZ
-
25
-
30
-
35
-
40
ns
3,4,5
Output Enable to Output in Low-Z
tOLZ
5
-
5
-
5
-
5
-
ns
Output Disable to Output in High-Z
tOHZ
-
25
-
25
-
30
-
35
ns
BLE, BHE Enable to Output in Low-Z
tBLZ
5
-
5
-
5
-
5
-
ns
4,5
BLE, BHE Disable to Output in High-Z
tBHZ
-
25
-
25
-
30
-
35
ns
3,4,5
BLE, BHE Access Time
tBA
-
35
-
40
-
40
-
50
ns
Read Cycle (9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 0
0C to +700C / -400C to +850C)
Write Cycle (11) (Vcc = 2.2 to2.7V, Gnd = 0V, T A = 0
0C to +700C / -400C to +850C)
Parameter
Symbol
Unit
Note
Write Cycle Time
tWC
55
-
70
-
85
-
100
-
ns
Chip Enable to Write End
tCW
50
-
60
-
70
-
80
-
ns
Address Setup to Write End
tAW
50
-
60
-
70
-
80
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
0
-
ns
Write Pulse Width
tWP
45
-
50
-
60
-
70
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Data Valid to Write End
tDW
25
-
30
-
35
-
40
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
0
-
ns
Write Enable to Output in High-Z
tWHZ
-
25
-
30
-
35
-
40
ns
Output Active from Write End
tOW
5
-
5
-
5
-
5
-
ns
BLE, BHE Setup to Write End
tBW
50
-
60
-
70
-
80
-
ns
Min Max Min Max Min Max Min Max
-55
-70
-85
-100
6
Min Max Min Max Min Max Min Max
-55
-70
-85
-100
REV. 1.3 OCT 2001 V62C2162048L(L)
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