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參數(shù)資料
| 型號： | V62C1802048L-100V |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, PLASTIC, STSOP-32 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 84K |
| 代理商： | V62C1802048L-100V |
V62C1802048L(L)
Data Retention Characteristics (L Version Only)(1)
Parameter
Symbol
Test Condition
Min
Max
Unit
VCC for Data Retention
VDR
CE1 > VCC - 0.2V or
1.0
-
V
Data Retention Current
ICCDR
CE2 < + 0.2V
1
A
Chip Deselect to Data Retention Time
tCDR
VIN > VCC - 0.2V or
0
-
ns
Operation Recovery Time(2)
tR
VIN < 0.2V
tRC
-
ns
Data Retention Mode
VDR > 1.0V
Vcc_typ
VIH
VDR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform (L Version Only) (TA = 0
0C to +700C / -400C to +850C)
7
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5
pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
REV. 1.2 May 2001 V62C1802048L(L)
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