
Thermal Resistance Table
Recommended Operating Conditions
Electrical Characteristics
SGLS322D – MAY 2006 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com
RESISTANCE
HIGH
LOW
θ
JC (°C/W)
130.9
148.1
θ
JA (°C/W)
205.6
347
MIN
MAX
UNIT
VDD
Supply voltage
1.6
6
V
VI
Input voltage
0
VDD + 0.3
V
VIH
High-level input voltage
0.7 × VDD
V
VIL
Low-level input voltage
0.3 × VDD
V
Δt/Δv
Input transition rise and fall rate at MR
100
ns/V
TA
Operating free-air temperature
–55
125
°C
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.3 V, IOH = –2 mA
RESET
(TPS3836)
VDD = 6 V, IOH = –3 mA
High-level output
VOH
0.8 × VDD
V
voltage
VDD = 2 V, IOH = –1 mA
RESET
(TPS3837)
VDD = 3.3 V, IOH = –2 mA
VDD = 2 V, IOL = 1 mA
RESET
(TPS3836/8)
VDD = 3.3 V, IOL = 2 mA
Low-level output
VOL
0.4
V
voltage
VDD = 3.3 V, IOL = 2 mA
RESET
(TPS3837)
VDD = 6 V, IOL = 3 mA
TPS3836/8
VDD ≥ 1.1 V, IOL = 50 A
0.2
Power-up reset
TA = 25°C
0.8 × VDD
V
voltage(1)
TPS3837
VDD ≥ 1.1 V, IOH = –50 A
TA = Full range
0.6 × VDD
TPS383xE18
1.64
1.71
1.73
TPS383xJ25
2.16
2.25
2.31
Negative-going
TPS383xH30
2.7
2.79
2.85
VIT
input threshold
V
TPS383xL30
2.54
2.64
2.71
voltage(2)
TA = 25°C
2.82
2.93
3.1
TPS383xK33
TA = Full range
2.72
2.93
3.2
1.7 V < VIT < 2.5 V
30
Vhys
Hysteresis at VDD input
2.5 V < VIT < 3.5 V
40
mV
3.5 V < VIT < 5 V
50
TA = 25°C
–30
–60
–90
MR (3)
MR = 0.7 × VDD, VDD = 6 V
A
High-level input
IIH
TA = Full range
–20
–60
–120
current
CT
CT = VDD = 6 V
–25
25
nA
TA = 25°C
–130
–200
–340
MR (3)
MR = 0 V, VDD = 6 V
A
Low-level input
IIL
TA = Full range
–90
–200
–350
current
CT
CT = 0 V, VDD = 6 V
–25
25
nA
High-level output
IOH
TPS3838
VDD = VIT + 0.2 V, VOH = VDD
25
nA
current
(1)
The lowest voltage at which RESET output becomes active, tr, VDD ≥ 15 s/V
(2)
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
F) should be placed near the supply terminal.
(3)
If manual reset is unused, MR should be connected to VDD to minimize current consumption.
6
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