- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄225499 > V58C2128404SBLT6I (PROMOS TECHNOLOGIES INC) 32M X 4 DDR DRAM, 0.7 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號： | V58C2128404SBLT6I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, PLASTIC, MS-024FC, TSOP2-66 |
| 文件頁數(shù)： | 4/60頁 |
| 文件大?。?/td> | 915K |
| 代理商： | V58C2128404SBLT6I |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
12
V58C2128(804/404/164)SB*I Rev. 1.3 March 2006
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SB*I
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and
BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can
be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Activation Timing
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-
cess variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre-
quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de-
layed and used to latch the output data into the receiving device. The tolerance for skew between DQS and
DQ (t
DQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK).
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
(CAS Latency = 2; Burst Length = Any)
tRRD(min)
tRP(min)
tRC
tRCD(min)
Begin Precharge Bank A
CK, CK
BA/Address
Command
Bank/Col
Read/A
Bank/Row
Activate/A
Activate/B
Pre/A
Bank/Row
Activate/A
Bank
Bank/Row
tRAS(min)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C365164S5 | 4M X 16 DDR DRAM, 0.1 ns, PDSO66 |
| V608ME06 | VCO, 1900 MHz - 2270 MHz |
| V603ME07 | VCO, 1896 MHz - 1924 MHz |
| V6049001 | VCO, 1600 MHz - 2200 MHz |
| V610ME04 | VCO, 1950 MHz - 2150 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C2128804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2256 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256324SAB30 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB30 |
| V58C2256324SAB33 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB33 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。