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參數(shù)資料
| 型號： | V58C2128164SBLS6 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | MO-233, FBGA-60 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 916K |
| 代理商： | V58C2128164SBLS6 |
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42
V58C2128(804/404/164)SB Rev. 2.2 March 2007
ProMOS TECHNOLOGIES
V58C2128(804/404/164)SB
NOTES: (continued)
43. Note 43 is not used.
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may
be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-
sistance is used between the VTT supply and the input pin.
45. Note 45 is not used.
46. tRAP t RCD.
47. Note 47 is not used.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO
REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F
except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed
by 200 clock cycles.
53. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
54. tDAL =(tWR/ tCK) + (tRP/ tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
For example: For DDR266B at CL=2.5 and tCK=7.5ns
tDAL=((15ns /7.5ns) + (20ns/ 7.5ns)) clocks=((2)+(3)) clocks=5 clocks
Max
imum
Nominal
high
Nominal low
Nominal
high
Minimum
Maxim
um
70
60
50
40
30
20
10
0.0
0.5
1.0
1.5
2.0
2.5
0.0
-120
-100
-80
-60
-40
-20
0
0.5
1.0
1.5
2.0
2.5
0
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