- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202172 > V55C3256164VGLK-7HPC (PROMOS TECHNOLOGIES INC) SYNCHRONOUS DRAM, PBGA54 PDF資料下載
參數(shù)資料
| 型號： | V55C3256164VGLK-7HPC |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封裝： | GREEN, MO-210, FBGA-54 |
| 文件頁數(shù)： | 54/55頁 |
| 文件大小： | 711K |
| 代理商： | V55C3256164VGLK-7HPC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當前第54頁第55頁
8
V55C3256164VG Rev. 1.0 September 2008
ProMOS TECHNOLOGIES
V55C3256164VG
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200
s is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register and Extended Mode Register Set
Command must be issued to initialize the Mode
Register. A minimum of two Auto Refresh cycles
(CBR) are also required.These may be done before
or after programming the Mode Register. Failure to
follow these steps may lead to unpredictable start-
up modes.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
rameters to be set as shown in the previous table.
Extended Mode Register
The extended Mode Register controls functions
beyond those controlled by the Mode Register.
These additional functions are unique to the mobile
SDRAM and includes the selection of drive strength
(DS). The device has four drive strength options:
Full, 1/2, 1/4 or 1/8. And a Partial-Array Self-Re-
fresh field (PASR). The PASR field is used to spec-
ify whether the partial bank 1/2, 1/4, 1/8, 1/16 or all
banks of the SDRAM array are enabled. Disabled
banks will not be refreshed in Self-Refresh mode
and written data will be lost. When only bank 0 is se-
lected, it’s possible to partially select only half or
more quarters of bank 0. The default setting for DS
is full strength, while PASR is full memory. Both DS
and PASR can be set during the initialization se-
quence and can be modified when the part is idle.
Additionally, the device has internal temperature
sensor control self refresh cycle automatically ac-
cording to the two temperature range; Max 40 deg
C, and Max. 85 deg C. This is the device internal
Temperature Compensated Self Refresh (TCSR).
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8 and full page. Column address-
es are segmented by the burst length and serial
data accesses are done within this boundary. The
first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are
generated automatically by the programmed burst
length and its sequence. For example, in a burst
length of 8 with interleave sequence, if the first ad-
dress is ‘2’, then the rest of the burst sequence is 3,
0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using se-
quential burst type. Full Page burst operation does
not terminate once the burst length has been
reached. (At the end of the page, it will wrap to the
start address and continue.) In other words, unlike
burst length of 2, 4, and 8, full page burst continues
until it is terminated using another command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V580MC04 | VCO, 850 MHz - 890 MHz |
| V707S001 | VCO, 500 MHz - 1000 MHz |
| V706S001 | VCO, 600 MHz - 1200 MHz |
| V583ME02 | VCO, 985 MHz - 1060 MHz |
| V580ME04 | VCO, 910 MHz - 1000 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V55HD | 制造商:Bugera 功能描述:55 WATT GUITAR AMPLIFIER 2 CHANNEL TUBE HEAD |
| V55MLA0402LN | 制造商:LITTELFUSE 制造商全稱:Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
| V55MLA0402N | 制造商:LITTELFUSE 制造商全稱:Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
| V55MLA0603H | 制造商:Littelfuse 功能描述: |
| V55MLA0603LN4 | 制造商:LITTELFUSE 制造商全稱:Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
發(fā)布緊急采購，3分鐘左右您將得到回復。