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參數(shù)資料
| 型號： | V54C316802VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Performance 3.3 Volt 2M X 8 Synchronous DRAM(3.3V高性能2Mx8同步動態(tài)RAM) |
| 中文描述： | 高性能3.3伏200萬× 8同步DRAM（3.3V的高性能2Mx8同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 1/60頁 |
| 文件大?。?/td> | 586K |
| 代理商： | V54C316802VB |
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MOSEL V ITELIC
1
V54C316802VB
HIGH PERFORMANCE
3.3 VOLT 2M X 8 SYNCHRONOUS DRAM
2 BANKS X 1MBit X 8
V54C316802VB Rev. 1.0 March 1998
PRELIMINARY
CAS Latency = 3
8
10
System Frequency (f
CK
)
125 MHz
100 MHz
Clock Cycle Time (t
CK3
)
8 ns
10 ns
Clock Access Time (t
AC3
)
6
7
Features
I
2 banks x 1Mbit x 8 organization
I
High speed data transfer rates up to 125 MHz
I
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I
Single Pulsed RAS Interface
I
Dual Data Mask for Byte Control
I
Dual Banks controlled by A11
I
Programmable CAS Latency: 2, 3
I
Programmable Wrap Sequence: Sequential or
Interleave
I
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
I
Multiple Burst Read with Single Write Operation
I
Automatic and Controlled Precharge Command
I
Random Column Address every CLK (1-N Rule)
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 44 Pin 400 mil TSOP-II
I
LVTTL Interface
I
Single +3.3 V
±
0.3 V Power Supply
I
-8 version for PC 100 applications.
(V54C316802VBT8PC)
The V54C316802VB is a dual bank Synchronous
DRAM organized as 2 banks x 1Mbit x 8. The
V54C316802VB achieves high speed data transfer
rates up to 125 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the two memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
8
10
Std.
0
°
C to 70
°
C
Blank
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