- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202171 > V54C3128404VBLI7 (PROMOS TECHNOLOGIES INC) 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 PDF資料下載
參數(shù)資料
| 型號： | V54C3128404VBLI7 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | GREEN, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 48/56頁 |
| 文件大?。?/td> | 734K |
| 代理商： | V54C3128404VBLI7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當(dāng)前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
52
V54C3128(16/80/40)4VB Rev.1.5 March 2006
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VB
Clock Enable (CKE) Truth Table:
Abbreviations:
RA = Row Address of Bank A
CA = Column Address of Bank A
BS = Bank Address
RB = Row Address of Bank B
CB = Column Address of Bank B
AP = Auto Precharge
RC = Row Address of Bank C
CC = Column Address of Bank C
RD = Row Address of Bank D
CD = Column Address of Bank D
Notes for SDRAM function truth table:
1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
STATE(n)
CKE
n-1
CKE
nCS
RAS
CAS
WE
Addr
ACTION
Self-Refresh6
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
INVALID
EXIT Self-Refresh, Idle after tRC
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
INVALID
EXIT Power-Down, > Idle.
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle7
H
L
H
L
X
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
X
Refer to the function truth table
Enter Power- Down
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V54C3128804VBLJ8PC | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| V54C3128404VBI8PC | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| V54C3128164VBI6 | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| V54C3128164VBS8PC | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| V54C3128804VAS7PC | 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3128404VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128404VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128804VAT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
| V54C3128804VAT7 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
| V54C3128804VAT8 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。