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| 型號： | V53C8126H50 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | ULTRA-HIGH PERFORMANCE, 128K X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 超高性能，128K的× 8位快速頁面模式的CMOS動態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 209K |
| 代理商： | V53C8126H50 |
1
PV53C8126H
V53C8126H Rev. 1.1 July 1997
MOSEL VITELIC
HIGH PERFORMANCE
35
40
45
50
Max.
RAS
Access Time, (t
RAC
)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
75 ns
80 ns
90 ns
V53C8126H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
Features
I
128K x 8-bit organization
I
RAS
access time: 35, 40, 45, 50 ns
I
Fast Page Mode supports sustained I/O data
rates up to 40 MHz
I
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh capability
I
Refresh Interval
V53C8126H – 512 cycles/8 ms
I
Available in 26/24 pin 300 mil SOJ and 28 pin
TSOP package
Description
The V53C8126H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8126H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 256
columns (x8) bits within a row with cycle times as
short as 21 ns. Because of static circuitry, the
CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8126H ideally suited for graphics,
digital signal processing and high performance
peripherals.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
35
40
45
50
Std.
0
°
C to 70
°
C
Blank
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