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參數(shù)資料
| 型號： | V53C364805A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 8M X 8 EDO Page Mode CMOS Dynamic RAM(3.3V 8Mx8 EDO頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 3.3伏8米× 8 EDO公司頁面模式的CMOS動態(tài)RAM（3.3 8Mx8 EDO公司頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 163K |
| 代理商： | V53C364805A |
6
V53C364805A Rev. 1.2 June 1998
MOSEL V ITELIC
AC Characteristics
(6,7,8)
V53C364805A
T
A
= 0 to 70 C,V
CC
= 3.3 V
±
0.3V
#
Symbol
Parameter
-40
- 50
- 60
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Common Parameters
1
t
RC
Random read or write cycle time
69
–
84
–
104
–
ns
2
t
RAS
RAS pulse width
40
100k
50
100k
60
100k
ns
3
t
CAS
CAS pulse width
6
10k
8
10k
10
10k
ns
4
t
RP
RAS precharge time
25
–
30
–
40
–
ns
5
t
CP
CAS precharge time
6
–
8
–
10
–
ns
6
t
ASR
Row address setup time
0
–
0
–
0
–
ns
7
t
RAH
Row address hold time
5
–
7
–
10
–
ns
8
t
ASC
Column address setup time
0
–
0
–
0
–
ns
9
t
CAH
Column address hold time
5
–
7
–
10
–
ns
10
t
RCD
RAS to CAS delay time
9
30
11
37
14
45
ns
11
t
RAD
RAS to column address delay
7
20
9
25
12
30
ns
12
t
RSH
RAS hold time
6
–
8
10
–
ns
13
t
CSH
CAS hold time
32
–
40
48
–
ns
14
t
CRP
CAS to RAS precharge time
5
–
5
–
5
–
ns
15
t
T
Transition time (rise and fall)
1
50
1
50
1
50
ns
7
16
t
REF
Refresh period for 8k-refresh
–
128
–
128
–
128
ms
Refresh period for L-version
–
256
–
256
–
256
ms
Read Cycle
17
t
RAC
Access time from RAS
–
40
–
50
–
60
ns
8, 9
18
t
CAC
Access time from CAS
–
10
–
13
–
15
ns
8, 9
19
t
CAA
Access time from column address
–
20
–
25
–
30
ns
8,10
20
t
OEA
OE access time
–
10
–
13
–
15
ns
8
21
t
RAL
Column address to RAS lead time
20
–
25
–
30
–
ns
22
t
RCS
Read command setup time
0
–
0
–
0
–
ns
23
t
RCH
Read command hold time
0
–
0
–
0
–
ns
11
24
t
RRH
Read command hold time referenced to RAS
0
–
0
–
0
–
ns
11
25
t
CLZ
CAS to output in low-Z
0
–
0
–
0
–
ns
8
26
t
OFF
Output buffer turn-off delay
0
10
0
13
0
15
ns
12
27
t
OEZ
Output buffer turn-off delay from OE
0
10
0
13
0
15
ns
12
28
t
DZC
Data to CAS low delay
0
–
0
–
0
–
0
29
t
DZO
Data to OE low delay
0
–
0
–
0
–
ns
13
30
t
CDD
CAS high to data delay
10
–
13
–
15
–
ns
14
31
t
ODD
OE high to data delay
10
–
13
–
15
–
ns
14
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