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參數(shù)資料
| 型號(hào)： | V23814-U1306-M136 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | PAROLI Tx AC, 1.6 Gbit/s |
| 中文描述： | 帕羅利得克薩斯州，交流1.6千兆/秒 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | V23814-U1306-M136 |
Fiber Optics
V23814/15-U1306-M130 Parallel Optical Link: PAROLI
Tx/Rx AC, 1.6 Gbit/s
6
Notes
1. Level Diagram:
2. |V
OD
|=|(output voltage of non-inverted output minus output voltage
of inverted output)|.
3. V
OS
=
1
/
2
(output voltage of inverted output + output voltage of non-
inverted output).
4. LVDS output must be terminated differentially with R
t
.
5. Measured between 20% and 80% level with a maximum capacitive
load of 5 pF
6. With no optical input jitter.
7 At sensitivity limit of -170 dBm at infinite ER.
8. Source current
9. Sink current
10.With input channel-to-channel skew 0 ps.
Parameter
Symbol Min.
Notes
Optical parameters valid for each channel.
1. Optical input data should be DC balanced within 100 ns. Maximum
time interval of consecutive ’0’s and ’1’s (run length) should not
exceed 50 ns.
2. Measured with a DC balanced pattern (within 144 bits) with a maxi-
mum run length of 72 bits. BER=10
–12
. Extinction ratio=infinite.
3. P
SDA
: Average optical power when SD switches from unactive to
active.
P
SDD
: Average optical power when SD switches from active to
unactive.
Figure 4. Timing diagram
Receiver Pin Description
Pin#
Pin Name
Typ.
Max.
Units
Data Rate
Per Channel
(
1)
D
R
250
1600
Mbit/s
Sensitivity
(Average Power)
(
2)
P
IN
–17.0 dBm
Saturation
(Average Power)
(
2)
P
SAT
–6.0
Signal Detect
Assert Level
(
3)
P
SDA
–18.0
Signal Detect
Deassert Level
(
3)
P
SDD
–26.0
Signal Detect
Hysteresis
(
3)
P
SDA
–
P
SDD
A
RL
1.0
2.5
4.0
dB
Return Loss of Receiver
12
mV
1475
925
Time
|VID|
t1
t2
Data Out 1, 12
Signal Detect 1
Signal Detect 12
Parameter
Symbol
Max.
Units
μ
s
Signal Detect
Deassert Time
t
1
10
Signal Detect
Assert Time
t
2
LVDS Output Enable off
Delay Time
t
3
20
ns
LVDS Output Enable on
Delay Time
t
4
Level/Logic Description
1
V
EE
V
CC1
Ground
2
Power supply voltage of
preamplifier
3
V
CC2
Power supply voltage of analog
circuitry
4
t.b.l.o.
to be left open
5
-RESET
LVCMOS In High=normal operation
Low=sets all Data Outputs
to low
This input has an internal
pull-up resistor which pulls to
high level when this input is
left open
6
SD1
LVCMOS
Out
Signal Dectect on fiber #1.
High=signal of sufficient AC
power is present on fiber #1
Low=signal on fiber #1 is
insufficient
7
V
CC3
Power supply voltage of
digital circuitry
8
V
EE
t.b.l.o.
Ground
9
to be left open
10
V
EE
V
EE
V
EE
DO01P
Ground
11
Ground
12
Ground
13
LVDS Out
Data Output #1, non-inverted
14
DO01N
LVDS Out
Data Output #1, inverted
15
V
EE
V
EE
DO02P
Ground
16
Ground
17
LVDS Out
Data Output #2, non-inverted
18
DO02N
LVDS Out
Data Output #2, inverted
19
V
EE
V
EE
DO03P
Ground
20
Ground
21
LVDS Out
Data Output #3, non-inverted
22
DO03N
LVDS Out
Data Output #3, inverted
t3
t4
LVDS Output Enable
Data Out
data valid
2.0 V
0.8 V
data Low
data valid
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