參數(shù)資料
型號(hào): V23814-K1306-M136
廠商: INFINEON TECHNOLOGIES AG
英文描述: PAROLI Tx AC, 1.25 Gbit/s
中文描述: 帕羅利得克薩斯州,交流1.25千兆位/秒
文件頁(yè)數(shù): 10/27頁(yè)
文件大?。?/td> 610K
代理商: V23814-K1306-M136
V23814-K1306-M136
V23815-K1306-M136
Description
Data Sheet
10
2001-12-01
Receiver V23815-K1306-M136
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, transimpedance amplifiers, and gain amplifiers. There are two different modules
available for LVDS and Infineon
s adjustable CML output. This description only refers to
a module with LVDS output. A module description for CML output can be provided
separately.
The data rate is up to 1250 Mbit/s for each channel. The receiver module
s min. data rate
of 500 Mbit/s is specified for the CID
1)
worst case pattern (disparity 72) or any pattern
with a lower disparity.
Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs
will not be effected.
All non data signals have LVCMOS levels.
Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns
for the receiver and approximately 5 ns per meter for the fiber optic cable.
Figure 3
Receiver Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Pin
Diode
Array
LVDS
Output
Stage
12
12
Data out
Data
Optical
Input
Electrical
Output
12
Gain
Amplifier
Signal
Detect
Circuit
12
Amplifier
Output Enable (OEN)
ENSD
SD1
-SD12
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