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參數(shù)資料
| 型號(hào)： | UT61256C |
| 英文描述： | ASYNCHRONOUS STATIC RAM- High Speed |
| 中文描述： | 異步靜態(tài)RAM高速 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | UT61256C |
UTRON
UT61256C
Rev. 1.4
32K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC.
P80031
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
WRITE CYCLE 1 (
Controlled) (1,2,3,5,6)
t WC
t AW
t CW
t AS
t WP
t WHZ
t OW
t DW
t DH
t WR
Address
CE
WE
Dout
Din
Data Valid
High-Z
(4)
WRITE CYCLE 2 ( CE Controlled) (1,2,5)
t WC
t AW
t CW
t AS
t WR
t WP
t WHZ
t DW
t DH
Data Valid
Address
CE
WE
Dout
Din
High-Z
Notes :
1.
WE and
CE must be HIGH during all address transitions.
2.
A write occurs during the overlap of a low CE and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off
and data to be placed on the bus.
4.
During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6.
tOW and tWHZ are specified with CL = 5pF. Transition is measured
500mV from steady state.
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