參數(shù)資料
型號(hào)： USS-820D
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁(yè)數(shù)： 24/58頁(yè)
文件大小： 868K
代理商： USS-820D
24
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 20. Endpoint Receive Status Register (RXSTAT)—Address: 0DH; Default: 0000 0000B
This register contains the current endpoint status of the receive FIFO specified by EPINDEX. This register is an
endpoint-indexed SFR.
* For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such
as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal
USB traffic, as documented in the USB specification, Section 8.6.
S = shared bit. P = PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section.
Bit 7
RXSEQ
R/W* (P
)
Bit 6
Bit 5
STOVW
R
Bit 4
EDOVW
R/W (S
)
Bit 3
Bit 2
RXVOID
Bit 1
RXERR
R
Bit 0
RXACK
RXSETUP
R/W (S
)
RXSOVW
W (P
)
Bit
7
Symbol
RXSEQ
Function/Description
Receiver Endpoint Sequence Bit (Read, Conditional Write).
* This bit is toggled on
completion of an ACK handshake in response to an OUT token. This bit is set (or
cleared) by hardware after reception of a SETUP token.
If the RXSOVW bit is set, this bit can be written by firmware when written along with the
new RXSEQ value.
Note:
Always verify this bit after writing to ensure that there is no conflict with hardware,
which may occur if a new SETUP token is received.
Received SETUP Token
. This bit is set by hardware when a valid SETUP token has
been received. When set, this bit causes received IN or OUT tokens to be NACKed until
the bit is cleared to allow proper data management for the transmit and receive FIFOs
from the previous transaction.
IN or OUT tokens are NACKed even if the endpoint is stalled (RXSTL or TXSTL) to allow
a control transaction to clear a stalled endpoint.
Firmware must clear this bit after it has finished reading out the SETUP packet and is
prepared for the next stage of the control transaction (data or status). For a stalled con-
trol endpoint, this bit should not be cleared until the RXSTL/TXSTL bits have been
cleared.
Start Overwrite Flag (Read Only).
This bit is set by hardware upon receipt of a SETUP
token for any control endpoint to indicate that the receive FIFO is being overwritten with
new SETUP data. When set, the FIFO state (RXFIF and read pointer) resets and is
locked for this endpoint until EDOVW is set. This prevents a prior, ongoing firmware read
from corrupting the read pointer as the receive FIFO is being cleared and new data is
being written into it. This bit is cleared by hardware at the end of handshake phase
transmission of the SETUP stage.
This bit is used only for control endpoints.
End Overwrite Flag.
This flag is set by hardware during the handshake phase of a
SETUP stage. It is set after every SETUP packet is received and must be cleared prior
to reading the contents of the FIFO. When set, the FIFO state (RXFIF and read pointer)
remains locked for this endpoint until this bit is cleared. This prevents a prior, ongoing
firmware read from corrupting the read pointer after the new data has been written into
the receive FIFO.
This bit is used only for control endpoints.
Receive Data Sequence Overwrite Bit.
* Writing a 1 to this bit allows the value of the
RXSEQ bit to be overwritten. Writing a 0 to this bit has no effect on RXSEQ. This bit
always returns 0 when read.
6
RXSETUP
5
STOVW
4
EDOVW
3
RXSOVW
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