- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383985 > USB3450-FZG (STANDARD MICROSYSTEMS CORP) HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE PDF資料下載
參數(shù)資料
| 型號(hào)： | USB3450-FZG |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE |
| 中文描述： | SERIAL COMM CONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220, QFN-40 |
| 文件頁數(shù)： | 33/40頁 |
| 文件大小： | 1086K |
| 代理商： | USB3450-FZG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
7.9
SMSC USB3450
33
Revision 0.1 (05-11-05)
DATASHEET
HS Detection Handshake – HS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to
Disable
Bit Stuffing and NRZI encoding
, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the downstream facing port. If the downstream facing port is HS capable then it will
begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the
chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it
will enter HS mode by setting TERMSELECT to HS mode (T7).
Figure 7.4
provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the
device port must terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note
that the sequence of Chirp K’s and Chirp J’s constitutes bus activity.
The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore
LINESTATE signal transitions must be used by the Link to step through the Chirp K-J-K-J-K-J state
diagram, where “K State” is equivalent to LINESTATE = K State and “J State” is equivalent to
LINESTATE = J State. The Link must employ a counter (Chirp Count) to count the number of Chirp K
and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus
state must be “continuously asserted for 2.5μs” must be verified by the Link sampling the LINESTATE
signals.
Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram
Detect K
Start Chirp
K-J-K-J-K-J
detection
INC Chirp
Count
K State
!K
Detect J
INC Chirp
Count
J State
!J
Chirp Count != 6
& !SE0
Chirp Count
= 0
Chirp Count != 6
& !SE0
Chirp Valid
Chirp
Invalid
SE0
Chirp Count
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| USB97C201 | USB 2.0 ATA/ ATAPI Controller |
| USB97C201-MC | USB 2.0 ATA/ ATAPI Controller |
| USB97C201-MN | USB 2.0 ATA/ ATAPI Controller |
| USB97CFDC-MN | USB FLOPPY DISK CONTROLLER |
| USB97C202 | ATA/ATAPI CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USB-3488A | 功能描述:數(shù)據(jù)記錄與采集 HIGH PERF IEEE-488 USB DAQ GPIB INT CON RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| USB3500 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface |
| USB3500-ABZJ | 功能描述:接口 - 專用 USB 2.0 PHY UTMI RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| USB3503 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications |
| USB3503A | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。