參數(shù)資料
型號: UPD78F9510GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 145/175頁
文件大?。?/td> 0K
描述: MCU 8BIT SGL CHIP 16PIN
標準包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
CHAPTER 4 PORT FUNCTIONS
User’s Manual U16994EJ6V0UD
69
(2) Port registers (P2 to P4)
These registers are used to write data to be output from the corresponding port pin to an external device
connected to the chip.
When a port register is read, the pin level is read in the input mode, and the value of the output latch of the
port is read in the output mode.
P20 to P23, P32, and P40 to P47 are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 4-9. Format of Port Register
Address: FF02H, After reset: 00H (Output latch) R/W
Symbol
7
6
5
4
3
2
1
0
P2
0
P23
P22
P21
P20
Address: FF03H, After reset: 00H
Note (Output latch) R/WNote
Symbol
7
6
5
4
3
2
1
0
P3
0
P34
0
P32
0
Address: FF04H, After reset: 00H (Output latch) R/W
Symbol
7
6
5
4
3
2
1
0
P4
P47
P46
P45
P44
P43
P42
P41
P40
m = 2 to 4; n = 0 to 7
Pmn
Controls of output data (in output mode)
Input data read (in input mode)
0
Output 0
Input low level
1
Output 1
Input high level
Note Because P34 is read-only, its reset value is undefined.
(3) Port mode control register 2 (PMC2) (
μPD78F921x only)
This register specifies the port/alternate function (except the A/D converter function) mode or the A/D
converter mode.
Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units.
PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PMC2 to 00H.
<R>
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