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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | UPD78F9222CS-CAC-A |
| 寤犲晢锛� | Renesas Electronics America |
| 鏂囦欢闋佹暩(sh霉)锛� | 111/125闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU 8BIT 4KB FLASH 20PIN |
| 妯欐簴鍖呰锛� | 400 |
| 绯诲垪锛� | 78K0S/Kx1+ |
| 鏍稿績铏曠悊鍣細 | 78K0S |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | LIN锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 15 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 4KB锛�4K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 256 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 鎵樼洡 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�鐣跺墠绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�
CHAPTER 5 CLOCK GENERATORS
User鈥檚 Manual U16898EJ6V0UD
84
Figure 5-12. Timing of Default Start by External Clock Input
VDD
(a)
(b)
External clock input
PCC = 02H, PPCC = 02H
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note)
Note Operation stop time is 277
渭s (MIN.), 544 渭s (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
Figure 5-13. Status Transition of Default Start by External Clock Input
HALT
STOP
HALT
instruction
STOP
instruction
VDD > 2.1 V (TYP.)
Start with PCC = 02H,
PPCC = 02H
Interrupt
Reset signal
Interrupt
Power
application
Reset by
power-on-clear
External clock input
selected by option byte
Clock division ratio
variable during
CPU operation
Remark
PCC:
Processor clock control register
PPCC: Preprocessor clock control register
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| UPD78F9234CS-CAA-A | MCU 8BIT 8KB FLASH 30PIN |
| UPD78F9418AGC-8BT-A | IC MCU 8BIT 32K FLASH 80QFP |
| USB-232-DIL | IC USB ASYNC SRL UART 28-DIL |
| USB-DAQ-DIL | IC SYSTEM DATA LOGGER 28-DIL |
| USB-FILESYS-DIL | IC SYSTEM USB FAT FILE 28-DIL |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| UPD78F9222MC | 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪:UPD78F9222MC |
| UPD78F9222MC(A)-5A4-A | 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪: |
| UPD78F9222MC(T)-5A4 | 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪: |
| UPD78F9222MC(T)-5A4-A | 鍒堕€犲晢:NEC Electronics Corporation 鍔熻兘鎻忚堪:8BIT MCU 4K FLASH 256B RAM 78F9222 鍒堕€犲晢:NEC Electronics Corporation 鍔熻兘鎻忚堪:8BIT MCU, 4K FLASH, 256B RAM, 78F9222 鍒堕€犲晢:NEC Electronics Corporation 鍔熻兘鎻忚堪:8BIT MCU, 4K FLASH, 256B RAM, 78F9222; Controller Family/Series:UPD78; Core Size:8bit; No. of I/O's:17; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Digital IC Case Style:SSOP; No. of Pins:20; Program Memory Size:4KB; RAM Memory ;RoHS Compliant: Yes |
| UPD78F9222MC-5A4-A | 鍔熻兘鎻忚堪:MCU 8BIT 4KB FLASH 20PIN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰帶鍒跺櫒锛� 绯诲垪:78K0S/Kx1+ 妯欐簴鍖呰:300 绯诲垪:78K0R/Ix3 鏍稿績铏曠悊鍣�:78K/0R 鑺珨灏哄:16-浣� 閫熷害:40MHz 閫ｉ€氭€�:3 绶� SIO锛孖²C锛孡IN锛孶ART/USART 澶栧湇瑷�(sh猫)鍌�:DMA锛孡VD锛孭OR锛孭WM锛學DT 杓稿叆/杓稿嚭鏁�(sh霉):27 绋嬪簭瀛樺劜鍣ㄥ閲�:16KB锛�16K x 8锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 澶у皬:- RAM 瀹归噺:1K x 8 闆诲 - 闆绘簮 (Vcc/Vdd):2.7 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄥ瀷:鍏�(n猫i)閮� 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:38-SSOP 鍖呰:鎵樼洡 |
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