μPD78F920x ONLY) User’s Manual U18172EJ3V0UD 116 6.4.5 PPG ou" />
參數(shù)資料
型號: UPD78F9202MA-CAC-A
廠商: Renesas Electronics America
文件頁數(shù): 22/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH 128B RAM
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 7
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LSSOP(0.225",5.72mm 寬)
包裝: 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (
μPD78F920x ONLY)
User’s Manual U18172EJ3V0UD
116
6.4.5
PPG output operations
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
<1>
Set the CRC00 register (see Figure 6-30 for the set value).
<2>
Set any value to the CR000 register as the cycle.
<3>
Set any value to the CR010 register as the duty factor.
<4>
Set the TOC00 register (see Figure 6-30 for the set value).
<5>
Set the count clock by using the PRM00 register.
<6>
Set the TMC00 register to start the operation (see Figure 6-30 for the set value).
Caution
Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
3. n = 0 or 1
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR000), respectively.
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