
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
920
(8/35)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
Be sure to clear bits 1 to 7 of PER1 to 0.
p.229
Controlling
high-speed
system
clock
High-speed
system clock
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition,
stop peripheral hardware that is operating on the high-speed system clock.
p.230
If switching the CPU/peripheral hardware clock from the high-speed system clock to
the internal high-speed oscillation clock after restarting the internal high-speed
oscillation clock, do so after 10
μs or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
for 10
μs.
p.231
Controlling
internal
high-speed
oscillation
clock
Internal high-
speed oscillation
clock
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation
clock.
p.232
Soft
XT1/P123,
XT2/P124
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
p.232
Hard
When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied
to
the
peripheral
hardware
(except
the
real-time
counter,
clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D
converter and IIC0 are not guaranteed.
For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
well
as
CHAPTER
29
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
pp.232,
233
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time.
For EXCLK and OSCSEL bits, see 6.6.1 (1) Example of setting
procedure when oscillating the X1 clock or 6.6.1 (2) Example of setting procedure
when using the external main system clock.
p.232
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
p.233
Subsystem
clock
control
Subsystem clock
The subsystem clock oscillation cannot be stopped using the STOP instruction.
p.233
pp.236,
Chapter
6
Soft
CPU clock
status
transition
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
237, 239
TCRmn:
Timer/counter
register mn
The count value is not captured to TDRmn even when TCRmn is read.
p.249
TDRmn: Timer
data register mn
TDRmn does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
p.251
Chapter
7
Soft
Timer
array unit
PER0:
Peripheral
enable register 0
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values (except for timer input select register m (TISm), input switch control
register (ISC), noise filter enable registers 1, 2 (NFEN1, 2), port mode registers 0, 1,
3, 4, 13, 14, 16 (PM0, PM1, PM3, PM4, PM13, PM14, PM16), and port registers 0, 1,
3, 4, 13, 14, 16 (P0, P1, P3, P4, P13, P14, P16)).
p.253