
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17893EJ8V0UD
75
Table 3-5. SFR List (5/5)
Manipulable Bit Range
Address
Special Function Register (SFR) Name
Symbol
R/W
1-bit
8-bit
16-bit
After Reset
FFFEEH
Priority specification flag register 11L
PR11L
R/W
√
FFH
FFFEFH
Priority specification flag register 11H
PR11H
PR11
R/W
√
FFH
FFFF0H
FFFF1H
Multiplication input data register A
MULA
R/W
√
0000H
FFFF2H
FFFF3H
Multiplication input data register B
MULB
R/W
√
0000H
FFFF4H
FFFF5H
Higher multiplication result storage register
MULOH
R
√
0000H
FFFF6H
FFFF7H
Lower multiplication result storage register
MULOL
R
√
0000H
FFFFEH
Processor mode control register
PMC
R/W
√
00H
Remark
For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.