參數(shù)資料
型號(hào)： UPD78F0535GC(S)-UBS-A
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 35/52頁(yè)
文件大?。?/td> 3774K
代理商： UPD78F0535GC(S)-UBS-A
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U17260EJ3V1UD
40
2.2.9 P120 to P124 (port 12)
P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input,
potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator
for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. The
following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode
register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
(2) Control mode
P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock
input for main system clock, and external clock input for subsystem clock.
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(f)
EXCLKS
This is an external clock input pin for subsystem clock.
Remark
Only for the
PD78F0537D, X1 and X2 can be used as on-chip debug mode setting pins (OCD0A,
OCD0B) when the on-chip debug function is used. For how to connect an in-circuit emulator
supporting on-chip debugging (QB-78K0MINI), see CHAPTER 27 ON-CHIP DEBUG FUNCTION
(
PD78F0537D ONLY).
2.2.10 P130 (port 13)
P130 functions as a 1-bit output-only port.
Remark
When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before
the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the
figure for Remark in 5.2.10 Port 13).
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