
Preliminary User’s Manual U17473EJ1V0UD
9
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1
Features .................................................................................................................................... 17
1.2
Applications ............................................................................................................................. 18
1.3
Ordering Information ............................................................................................................... 19
1.4
Pin Configuration (Top View).................................................................................................. 20
1.5
78K0/Lx2 Series Lineup........................................................................................................... 23
1.6
Block Diagram .......................................................................................................................... 25
1.7
Outline of Functions ................................................................................................................ 26
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 29
2.1
Pin Function List...................................................................................................................... 29
2.2
Description of Pin Functions .................................................................................................. 33
2.2.1
P00 to P06 (port 0).....................................................................................................................33
2.2.2
P10 to P17 (port 1).....................................................................................................................34
2.2.3
P20 to P27 (port 2).....................................................................................................................35
2.2.4
P30 to P33 (port 3).....................................................................................................................35
2.2.5
P70 to P77 (port 7).....................................................................................................................36
2.2.6
P120 to P124 (port 12)...............................................................................................................36
2.2.7
SDA0..........................................................................................................................................37
2.2.8
SCL0 ..........................................................................................................................................37
2.2.9
AVREF .........................................................................................................................................37
2.2.10
AVSS ...........................................................................................................................................37
2.2.11
S0 to S39 ...................................................................................................................................37
2.2.12
COM0 to COM3 .........................................................................................................................37
2.2.13
LVDD ...........................................................................................................................................37
2.2.14
LVSS ...........................................................................................................................................37
2.2.15
VLC0 to VLC2 ................................................................................................................................37
2.2.16
CAPH, CAPL..............................................................................................................................37
2.2.17
RESET .......................................................................................................................................37
2.2.18
REGC.........................................................................................................................................38
2.2.19
VDD .............................................................................................................................................38
2.2.20
VSS .............................................................................................................................................38
2.2.21
FLMD0 .......................................................................................................................................38
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins....................................... 39
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 43
3.1
Memory Space.......................................................................................................................... 43
3.1.1
Internal program memory space ................................................................................................48
3.1.2
Bank area (
PD78F0397 and 78F0397D only)..........................................................................50
3.1.3
Internal data memory space.......................................................................................................51
3.1.4
Special function register (SFR) area ..........................................................................................52
3.1.5
Data memory addressing ...........................................................................................................52
3.2
Processor Registers ................................................................................................................ 56
3.2.1
Control registers.........................................................................................................................56