參數(shù)資料
型號： UPD78F0361GB(T)-UEU-A
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, LEAD FREE, FINE PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 17/32頁
文件大?。?/td> 3542K
代理商： UPD78F0361GB(T)-UEU-A
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17734EJ1V0UD
24
1.7 Outline of Functions
(1/2)
Item
μPD78F0361
μPD78F0362
μPD78F0363
μPD78F0363D
Flash memory
(self-programming
supported)
Note1
16 KB
24 KB
32 KB
High-speed RAM
Note1
768 bytes
1 KB
Internal
memory
LCD display RAM
20
× 4 bits
Memory space
64 KB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V,
1 to 5 MHz: VDD = 1.8 to 5.5 V
Main system
clock
(oscillation
frequency)
Internal high-speed
oscillation clock
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(oscillation frequency)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(for TMH1, WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose registers
8 bits
× 32 registers (8 bits × 8 registers × 4 banks)
0.1
μs (high-speed system clock: @ fXH = 20 MHz operation)
0.25
μs (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation)
Minimum instruction execution time
122
μs (subsystem clock: @ fSUB = 32.768 kHz operation)
Instruction set
8-bit operation, 16-bit operation
Multiply/divide (8 bits
× 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, and Boolean operation)
BCD adjust, etc.
I/O ports
CMOS I/O: 24
Timers
16-bit timer/event counter: 1 channel
8-bit timer/event counter: 2 channels
8-bit timer:
2 channels
Watch timer:
1 channel
Watchdog timer:
1 channel
Timer outputs
5 (PWM output: 4, PPG output: 1)
Clock output
156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: @ fPRS = 20 MHz operation)
32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation)
A/D converter
10-bit resolution
× 5 channels (AVREF = 2.3 to 5.5 V)
Serial interface
UART supporting LIN-bus: 1 channel
3-wire serial I/O/UART
Note2: 1 channel
I
2C bus:
1 channel
Notes 1.
The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
2.
Select either of the functions of these alternate-function pins.
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