![](http://datasheet.mmic.net.cn/370000/UPD784915A_datasheet_16743933/UPD784915A_3.png)
μ
PD784915A, 784916A
3
Function List (1/2)
Item
Internal ROM capacity
Internal RAM capacity
Operating clock
Minimum instruction ex-
ecution time
I/O ports
Real-time output port
Timer/counter
Capture register
VCR special circuit
General-purpose
timer
PWM output
Serial interface
A/D converter
μ
PD784915A
μ
PD784916A
48 Kbytes
1280 bytes
16 MHz (internal clock: 8 MHz)
Low frequency oscillation mode: 8 MHz (internal clock: 8 MHz)
Low power dissipation mode: 32.768 kHz (subsystem clock)
250 ns (with 8-MHz internal system clock)
64 Kbytes
input : 8
54
I/O
: 46
11 (including one each for pseudo V
SYNC
, head amplifier switch, and chrominance
rotation)
Timer/counter
Compare register
Capture register
TM0 (16 bits)
3
TM1 (16 bits)
3
FRC (22 bits)
-
TM3 (16 bits)
2
UDC (5 bits)
1
EC (8 bits)
4
EDV (8 bits)
1
Input signal
Number of bits
Measurable cycle
CFG
22
125 ns to 524 ms
DFG
22
125 ns to 524 ms
HSW
16
1
μ
s to 65.5 ms
V
SYNC
22
125 ns to 524 ms
CTL
16
1
μ
s to 65.5 ms
T
REEL
22
125 ns to 524 ms
S
REEL
22
125 ns to 524 ms
V
SYNC
separation circuit, H
SYNC
separation circuit
VISS detection, wide aspect detection circuits
Field identification circuit
Head amplifier switch/chroma rotation output circuit
Timer
Compare register
TM2 (16 bits)
1
TM4 (16 bits)
1 (capture/compare)
TM5 (16 bits)
1
16-bit accuracy : 3 channels (carrier frequency: 62.5 kHz)
8-bit accuracy
: 3 channels (carrier frequency: 62.5 kHz)
3-wire serial I/O: 2 channels
BUSY/STRB control (1 channel only)
8-bit resolution x 12 channels, conversion time: 10
μ
s
Remark
-
1
6
1
-
-
-
For HSW signal generation
For CFG signal division
Operating edge
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
Capture register
-
1
-
Super
timer
unit