參數(shù)資料
型號： UPD784915A
廠商： NEC Corp.
英文描述： 16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16位單晶片微控制器
文件頁數(shù)： 69/86頁
文件大?。?/td> 446K
代理商： UPD784915A
μ
PD784915A, 784916A
69
Other operations (T
A
= –10 to +70
°
C, V
DD
= AV
DD
= 4.5 to 5.5 V, V
SS
= AV
SS
= 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Timer input signal low-level width
t
WCTL
When DFGIN, CFGIN, DPGIN, REEL0IN,
t
CLK1
ns
or REEL1IN logic level is input
Timer input signal high-level width
t
WCTH
When DFGIN, CFGIN, DPGIN, REEL0IN,
t
CLK1
ns
or REEL1IN logic level is input
Timer input signal valid edge input cycle
t
PERIN
When DFGIN, CFGIN, or DPGIN is input
2
μ
s
CSYNCIN low-level width
t
WCR1L
When digital noise elimination circuit is not used
8t
CLK1
ns
When digital noise elimination circuit is used
108t
CLK1
ns
(Bit 4 of INTM2 = 0)
When digital noise elimination circuit is used
180t
CLK1
ns
(Bit 4 of INTM2 = 1)
CSYNCIN high-level width
t
WCR1H
When digital noise elimination circuit is not used
8t
CLK1
ns
When digital noise elimination circuit is used
108t
CLK1
ns
(Bit 4 of INTM2 = 0)
When digital noise elimination circuit is used
180t
CLK1
ns
(Bit 4 of INTM2 = 1)
Digital noise
Eliminated pulse width
t
WSEP
Bit 4 of INTM2 = 0
104t
CLK1
ns
elimination
Bit 4 of INTM2 = 1
176t
CLK1
ns
circuit
Passed pulse width
Bit 4 of INTM2 = 0
108t
CLK1
ns
Bit 4 of INTM2 = 1
180t
CLK1
ns
NMI low-level width
t
WNIL
V
DD
= AV
DD
= 2.7 to 5.5 V
10
μ
s
μ
s
NMI high-level width
t
WNIH
V
DD
= AV
DD
= 2.7 to 5.5 V
10
INTP0, INTP3 low-level widths
t
WIPL0
2t
CLK1
ns
INTP0, INTP3 high-level widths
t
WIPH0
2t
CLK1
ns
INTP1, KEY0-KEY4 low-level widths
t
WIPL1
Mode other than STOP mode
2t
CLK1
ns
In STOP mode, for releasing STOP mode
10
μ
s
INTP1, KEY0-KEY4 high-level widths
t
WIPH1
Mode other than STOP mode
2t
CLK1
ns
In STOP mode, for releasing STOP mode
10
μ
s
INTP2 low-level width
t
WIPL2
In normal mode,
Sampling = f
CLK
2t
CLK1
32
Note
ns
with main clock
Sampling = f
CLK
/128
μ
s
μ
s
Normal mode,
Sampling = f
CLK
61
with subclock
Sampling = f
CLK
/128
7.9
Note
ms
In STOP mode, for releasing STOP mode
10
μ
s
INTP2 high-level width
t
WIPH2
In normal mode,
Sampling = f
CLK
2t
CLK1
32
Note
ns
with main clock
Sampling = f
CLK
/128
μ
s
μ
s
Normal mode,
Sampling = f
CLK
61
with subclock
Sampling = f
CLK
/128
7.9
Note
ms
In STOP mode, for releasing STOP mode
10
μ
s
μ
s
RESET low-level width
t
WRSL
10
Note
If a high or low level is successively input two times during the sampling period, a high or low level is
detected.
Remark
t
CKL1
: operating clock cycle time of peripheral circuit (125 ns)
相關(guān)PDF資料
PDF描述
UPD784915AGF 16-BIT SINGLE-CHIP MICROCONTROLLERS
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UPD784915B 16-BIT SINGLE-CHIP MICROCONTROLLERS
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