參數(shù)資料
型號(hào)： UPD78218A
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述： 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁(yè)數(shù)： 48/66頁(yè)
文件大小： 510K
代理商： UPD78218A
48
μ
PD78217A, 78218A
PARAMETER
SYMBOL
FORMULA
MIN./MAX.
12 MHz
UNIT
X1 input clock cycle time
t
CYX
MIN.
82
ns
Address setup time (to ASTB
↓
)
t
SAST
t
CYX
– 30
MIN.
52
ns
RD
↓
delay time from address
t
DAR
2t
CYX
– 35
MIN.
129
ns
Address float time (from RD
↓
)
t
FAR
t
CYX
/2 – 30
MIN.
11
ns
Data input time from address
t
DAID
(4 + 2n) t
CYX
– 100
MAX.
228
Note
ns
Data input time from ASTB
↓
t
DSTID
(3 + 2n) t
CYX
– 65
MAX.
181
Note
ns
Data input time from RD
↓
t
DRID
(2 + 2n) t
CYX
– 64
MAX.
100
Note
ns
RD
↓
delay time from ASTB
↓
t
DSTR
t
CYX
– 30
MIN.
52
ns
Address active time from RD
↑
t
DRA
2t
CYX
– 40
MIN.
124
ns
ASTB
↑
delay time from RD
↑
t
DRST
2t
CYX
– 40
MIN.
124
ns
RD low-level width
t
WRL
(2 + 2n) t
CYX
– 40
MIN.
124
Note
ns
ASTB high-level width
t
WSTH
t
CYX
– 30
MIN.
52
ns
WR
↓
delay time from address
t
DAW
2t
CYX
– 35
MIN.
129
ns
Data output time from ASTB
↓
t
DSTOD
t
CYX
+ 60
MAX.
142
ns
t
CYX
– 30
(Refreshing disabled)
2t
CYX
– 35
(Refreshing enabled)
Data setup time (to WR
↑
)
t
SODWR
(3 + 2n) t
CYX
– 100
MIN.
146
Note
ns
t
CYX
– 60
(Refreshing enabled)
ASTB
↑
delay time from WR
↑
t
DWST
t
CYX
– 40
MIN.
42
ns
(3 + 2n) t
CYX
– 50
(Refreshing disabled)
(2 + 2n) t
CYX
– 50
(Refreshing enabled)
WAIT
↓
input time from address
t
DAWT
3t
CYX
– 100
MAX.
146
ns
WAIT
↓
input time from ASTB
↓
t
DSTWT
2t
CYX
– 80
MAX.
84
ns
t
WWL1
MIN.
196
Note
ns
t
WWL2
MIN.
114
Note
ns
WR low-level width
t
CYX
DEPENDENT BUS TIMING DEFINITION (1/2)
Data setup time (to WR
↓
)
t
SODWF
MIN.
22
ns
WR
↓
delay time from ASTB
↓
t
DSTW1
MIN.
52
ns
t
DSTW2
MIN.
129
ns
Remark
"n" indicates the number of waits.
Note
When n = 0
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