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參數(shù)資料
| 型號： | UPD780032AYGK |
| 廠商： | NEC Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 27/70頁 |
| 文件大?。?/td> | 527K |
| 代理商： | UPD780032AYGK |
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27
μ
PD780031AY, 780032AY, 780033AY, 780034AY
Data Sheet U14045EJ1V0DS00
(3) Serial interface IIC0
The serial interface IIC0 has the I
2
C (Inter IC) bus mode (multimaster supported).
I
2
C bus mode (multimaster supported)
This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and serial data bus line (SDA0).
This mode complies with the I
2
C bus format, and can output "start condition", "data", and "stop condition"
during transmission via the serial data bus. This data is automatically detected by hardware during
reception.
Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the
serial data bus line are required.
Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
Noise elimination
circuit
Noise elimination
circuit
Matched
signal
IIC shift register 0
(IIC0)
SO0 latch
IICE0
D
SET
CLEAR
CL00
SDA0/P32
SCL0/P33
N-ch open-
drain output
Data hold
time correction
circuit
Acknowledge
detection
circuit
Wake-up control
circuit
Acknowledge
detection circuit
Stop condition
detection circuit
Serial clock counter
Interrupt request
signal generator
Serial clock control circuit
N-ch open-drain
output
Serial clock wait
control circuit
Prescaler
INTIIC0
f
X
CLD0
IIC transfer clock select
register 0 (IICCL0)
Internal bus
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
MSTS0
ALD0 EXC0
COI0
TRC0
ACKD0
STD0 SPD0
Start condition
detection circuit
DAD0 SMC0 DFC0 CL00
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