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參數(shù)資料
| 型號： | UPD77019-013 |
| 廠商： | NEC Corp. |
| 英文描述： | PTSE 5C 5#16 PIN PLUG |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 1/56頁 |
| 文件大小： | 261K |
| 代理商： | UPD77019-013 |
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The
μ
PD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal
processing with its demand for high speed and precision.
The
μ
PD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask
code ordering process. Also the
μ
PD77019-013 can operate as simplified evaluate chip for as the
μ
PD7701x family.
About mask ROM and mask option, there are following differences between the
μ
PD77019-013 and
μ
PD77019.
MOS INTEGRATED CIRCUIT
μ
PD77019-013
16 bits, Fixed-point Digital Signal Processor
Document No. U13053EJ1V0DS00 (1st edition)
Date Published March 1998 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
μ
PD77019
Variable multiple rate (1, 2, 3, 4, 8) by mask
option
Enable (PLL clock multiple rate is set to 1 by
mask option.)
External clock is connected to the X1 pin.
Crystal is connected between the X1 pin and
X2 pin.
Low level fixed, or internal system clock
output is selectable by mask option.
Coding user program or data when ordering
mask ROM.
Enable to boot from internal data ROM or
external data area.
μ
PD77019-013
Fixed to 4
Disable (PLL clock multiple rate is fixed to 4.)
External clock is connected to the X1 pin.
Leave the X2 pin open.
Output internal system clock.
Not available (already masked by the void
code)
Enable to boot from external data area (Boot
information data is masked.) Refer to
2.6
Boot Function
.
PLL clock multiple rate
Crystal resonator
connection
Clock Input pin
Clock output pin
Internal mask ROM
Self boot
ORDERING INFORMATION
Part Number
Package
μ
PD77019GC-013-9EU
100-pin plastic TQFP (FINE PITCH) (14
×
14 mm)
1998
PRELIMINARY DATA SHEET
The
μ
PD7701x family consists of the
μ
PD77016, 77015, 77017, 77018, 77018A and
μ
PD77019.
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