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參數(shù)資料
| 型號： | UPD75P216A |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 281K |
| 代理商： | UPD75P216A |
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μ
PD75P216A
16
t
CY
AC Characteristics (T
a
= –10 to +70
°
C, V
DD
= +5 V
±
10%)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Main system clock
0.95
32
μ
s
Subsystem clock
114
122
125
μ
s
TI0 input frequency
f
TI
0
0.6
MHz
TI0 input high- and low-level width
t
TIH
, t
TIL
0.83
μ
s
Input
0.8
μ
s
Output
0.95
μ
s
Input
0.4
μ
s
Output
t
KCY
/2-50
ns
SI setup time (to SCK
↑
)
t
SIK
100
ns
SI hold time (to SCK
↑
)
t
KSI
400
ns
SCK
↓ →
SO output delay time
t
KSO
300
ns
INT0
Note 2
μ
s
INT1
2t
CY
μ
s
INT2, 4
10
μ
s
RESET low-level width
t
RSL
10
μ
s
Note 1.
The CPU clock () cycle time is decided by the oscillation frequency of the resonator, system clock
control register (SCC), and processor clock control register (PCC).
The figure to the right indicates cycle time (t
CY
) characteristics for supply voltage V
DD
when using the
main system clock.
2.
This is 2t
CY
or 128/f
XX
according to the interrupt mode register setting (IM0).
t
CY
vs V
DD
(Main system clock)
CPU clock time
Note 1
(minimum instruction
execution time = 1 machine cycle)
SCK cycle time
t
KCY
SCK high- and low-level width
t
KH
, t
KL
Interrupt inputs
high- and low-level width
t
INTH
,
t
INTL
50
10
5
1
0.5
0
1
2
3
4
5
6
Guaranteed
operating range
Power supply voltage V
DD
[V]
C
C
μ
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