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參數(shù)資料
| 型號： | UPD754264 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁數(shù)： | 28/68頁 |
| 文件大?。?/td> | 318K |
| 代理商： | UPD754264 |
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28
μ
PD754264
9. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
μ
PD754264.
Table 9-1. Operation Status in Standby Mode
Item
Mode
STOP Mode
HALT Mode
Set instruction
Operation
status
STOP instruction
Operation stops.
HALT instruction
Only the CPU clock
Φ
halts (oscillation
continues).
Clock generator
Basic interval timer/
watchdog timer
Operation stops.
Operable
BT mode: The IRQBT is set in the basic
time interval.
WT mode: Reset is generated by the
BT overflow.
Timer counter
Operation stops.
Operable.
External interrupt
INT0 is not operable.
Note
INT2 is operable during KRn falling period only.
CPU
The operation stops.
Release signal
Reset signal
Interrupt request signal sent from
interrupt enabled peripheral hardware
System reset signal (key return reset)
generated by KRn falling edge when the
KRREN pin = 1
Reset signal
Interrupt request signal sent from
interrupt enabled peripheral hardware
Note
Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register
(IM0).
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